slice_chunk_size  271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size);
slice_chunk_size  473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.slice_chunk_size            = 0;
slice_chunk_size  572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		CHUNK_SIZE, reg_vals->pps.slice_chunk_size);
slice_chunk_size   70 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->slice_chunk_size         = from->slice_chunk_size;
slice_chunk_size  125 drivers/gpu/drm/drm_dsc.c 	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
slice_chunk_size  274 drivers/gpu/drm/drm_dsc.c 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 *
slice_chunk_size  283 drivers/gpu/drm/drm_dsc.c 		vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
slice_chunk_size  301 drivers/gpu/drm/drm_dsc.c 	slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height;
slice_chunk_size  731 drivers/gpu/drm/i915/display/intel_vdsc.c 	pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
slice_chunk_size 11491 drivers/gpu/drm/i915/i915_reg.h #define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
slice_chunk_size  236 include/drm/drm_dsc.h 	u16 slice_chunk_size;