slice_bpg_offset  279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset);
slice_bpg_offset  484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.slice_bpg_offset            = 0;
slice_bpg_offset  596 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset);
slice_bpg_offset   67 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->slice_bpg_offset         = from->slice_bpg_offset;
slice_bpg_offset  172 drivers/gpu/drm/drm_dsc.c 	pps_payload->slice_bpg_offset =
slice_bpg_offset  173 drivers/gpu/drm/drm_dsc.c 		cpu_to_be16(dsc_cfg->slice_bpg_offset);
slice_bpg_offset  349 drivers/gpu/drm/drm_dsc.c 	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size -
slice_bpg_offset  364 drivers/gpu/drm/drm_dsc.c 				vdsc_cfg->slice_bpg_offset) *
slice_bpg_offset  649 drivers/gpu/drm/i915/display/intel_vdsc.c 	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
slice_bpg_offset  218 include/drm/drm_dsc.h 	u16 slice_bpg_offset;
slice_bpg_offset  439 include/drm/drm_dsc.h 	__be16 slice_bpg_offset;