SMUIO_BASE         53 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
SMUIO_BASE         48 drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
SMUIO_BASE         48 drivers/gpu/drm/amd/amdgpu/navi12_reg_init.c 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
SMUIO_BASE         48 drivers/gpu/drm/amd/amdgpu/navi14_reg_init.c 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
SMUIO_BASE         50 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
SMUIO_BASE         49 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
SMUIO_BASE        199 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
SMUIO_BASE        115 drivers/gpu/drm/amd/include/navi10_ip_offset.h static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },
SMUIO_BASE        158 drivers/gpu/drm/amd/include/navi12_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
SMUIO_BASE        158 drivers/gpu/drm/amd/include/navi14_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0 } },
SMUIO_BASE        193 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0 } },
SMUIO_BASE        193 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE SMUIO_BASE			= { { { { 0x00016800, 0, 0, 0, 0 } },
SMUIO_BASE        123 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE SMUIO_BASE            ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } },