sirfsoc_timer_base   53 drivers/clocksource/timer-atlas7.c static void __iomem *sirfsoc_timer_base;
sirfsoc_timer_base   58 drivers/clocksource/timer-atlas7.c 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
sirfsoc_timer_base   59 drivers/clocksource/timer-atlas7.c 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
sirfsoc_timer_base   65 drivers/clocksource/timer-atlas7.c 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
sirfsoc_timer_base   66 drivers/clocksource/timer-atlas7.c 		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
sirfsoc_timer_base   76 drivers/clocksource/timer-atlas7.c 	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
sirfsoc_timer_base   91 drivers/clocksource/timer-atlas7.c 	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
sirfsoc_timer_base   92 drivers/clocksource/timer-atlas7.c 			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
sirfsoc_timer_base   94 drivers/clocksource/timer-atlas7.c 	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
sirfsoc_timer_base   95 drivers/clocksource/timer-atlas7.c 	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
sirfsoc_timer_base  108 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
sirfsoc_timer_base  110 drivers/clocksource/timer-atlas7.c 	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
sirfsoc_timer_base  131 drivers/clocksource/timer-atlas7.c 		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
sirfsoc_timer_base  139 drivers/clocksource/timer-atlas7.c 		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
sirfsoc_timer_base  142 drivers/clocksource/timer-atlas7.c 		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
sirfsoc_timer_base  144 drivers/clocksource/timer-atlas7.c 		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
sirfsoc_timer_base  146 drivers/clocksource/timer-atlas7.c 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
sirfsoc_timer_base  147 drivers/clocksource/timer-atlas7.c 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
sirfsoc_timer_base  243 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
sirfsoc_timer_base  244 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
sirfsoc_timer_base  245 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
sirfsoc_timer_base  248 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
sirfsoc_timer_base  249 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
sirfsoc_timer_base  250 drivers/clocksource/timer-atlas7.c 	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
sirfsoc_timer_base  251 drivers/clocksource/timer-atlas7.c 		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
sirfsoc_timer_base  252 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
sirfsoc_timer_base  253 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
sirfsoc_timer_base  256 drivers/clocksource/timer-atlas7.c 	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
sirfsoc_timer_base  265 drivers/clocksource/timer-atlas7.c 	sirfsoc_timer_base = of_iomap(np, 0);
sirfsoc_timer_base  266 drivers/clocksource/timer-atlas7.c 	if (!sirfsoc_timer_base) {
sirfsoc_timer_base   55 drivers/clocksource/timer-prima2.c static void __iomem *sirfsoc_timer_base;
sirfsoc_timer_base   62 drivers/clocksource/timer-prima2.c 	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
sirfsoc_timer_base   66 drivers/clocksource/timer-prima2.c 	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
sirfsoc_timer_base   80 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
sirfsoc_timer_base   81 drivers/clocksource/timer-prima2.c 	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
sirfsoc_timer_base   83 drivers/clocksource/timer-prima2.c 		readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
sirfsoc_timer_base   94 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
sirfsoc_timer_base   95 drivers/clocksource/timer-prima2.c 	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
sirfsoc_timer_base   97 drivers/clocksource/timer-prima2.c 	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
sirfsoc_timer_base   99 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
sirfsoc_timer_base  100 drivers/clocksource/timer-prima2.c 	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
sirfsoc_timer_base  107 drivers/clocksource/timer-prima2.c 	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
sirfsoc_timer_base  110 drivers/clocksource/timer-prima2.c 		       sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
sirfsoc_timer_base  116 drivers/clocksource/timer-prima2.c 	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
sirfsoc_timer_base  118 drivers/clocksource/timer-prima2.c 	writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
sirfsoc_timer_base  127 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
sirfsoc_timer_base  131 drivers/clocksource/timer-prima2.c 			readl_relaxed(sirfsoc_timer_base +
sirfsoc_timer_base  141 drivers/clocksource/timer-prima2.c 			sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
sirfsoc_timer_base  144 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
sirfsoc_timer_base  146 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
sirfsoc_timer_base  215 drivers/clocksource/timer-prima2.c 	sirfsoc_timer_base = of_iomap(np, 0);
sirfsoc_timer_base  216 drivers/clocksource/timer-prima2.c 	if (!sirfsoc_timer_base) {
sirfsoc_timer_base  224 drivers/clocksource/timer-prima2.c 		sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
sirfsoc_timer_base  225 drivers/clocksource/timer-prima2.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
sirfsoc_timer_base  226 drivers/clocksource/timer-prima2.c 	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
sirfsoc_timer_base  227 drivers/clocksource/timer-prima2.c 	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);