simd 706 arch/arm/crypto/aes-ce-glue.c struct simd_skcipher_alg *simd; simd 724 arch/arm/crypto/aes-ce-glue.c simd = simd_skcipher_create_compat(algname, drvname, basename); simd 725 arch/arm/crypto/aes-ce-glue.c err = PTR_ERR(simd); simd 726 arch/arm/crypto/aes-ce-glue.c if (IS_ERR(simd)) simd 729 arch/arm/crypto/aes-ce-glue.c aes_simd_algs[i] = simd; simd 512 arch/arm/crypto/aes-neonbs-glue.c struct simd_skcipher_alg *simd; simd 533 arch/arm/crypto/aes-neonbs-glue.c simd = simd_skcipher_create_compat(algname, drvname, basename); simd 534 arch/arm/crypto/aes-neonbs-glue.c err = PTR_ERR(simd); simd 535 arch/arm/crypto/aes-neonbs-glue.c if (IS_ERR(simd)) simd 538 arch/arm/crypto/aes-neonbs-glue.c aes_simd_algs[i] = simd; simd 1028 arch/arm64/crypto/aes-glue.c struct simd_skcipher_alg *simd; simd 1050 arch/arm64/crypto/aes-glue.c simd = simd_skcipher_create_compat(algname, drvname, basename); simd 1051 arch/arm64/crypto/aes-glue.c err = PTR_ERR(simd); simd 1052 arch/arm64/crypto/aes-glue.c if (IS_ERR(simd)) simd 1055 arch/arm64/crypto/aes-glue.c aes_simd_algs[i] = simd; simd 529 arch/arm64/crypto/aes-neonbs-glue.c struct simd_skcipher_alg *simd; simd 550 arch/arm64/crypto/aes-neonbs-glue.c simd = simd_skcipher_create_compat(algname, drvname, basename); simd 551 arch/arm64/crypto/aes-neonbs-glue.c err = PTR_ERR(simd); simd 552 arch/arm64/crypto/aes-neonbs-glue.c if (IS_ERR(simd)) simd 555 arch/arm64/crypto/aes-neonbs-glue.c aes_simd_algs[i] = simd; simd 240 crypto/simd.c struct simd_skcipher_alg *simd; simd 252 crypto/simd.c simd = simd_skcipher_create_compat(algname, drvname, basename); simd 253 crypto/simd.c err = PTR_ERR(simd); simd 254 crypto/simd.c if (IS_ERR(simd)) simd 256 crypto/simd.c simd_algs[i] = simd; simd 490 crypto/simd.c struct simd_aead_alg *simd; simd 502 crypto/simd.c simd = simd_aead_create_compat(algname, drvname, basename); simd 503 crypto/simd.c err = PTR_ERR(simd); simd 504 crypto/simd.c if (IS_ERR(simd)) simd 506 crypto/simd.c simd_algs[i] = simd; simd 623 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t offset, se, sh, cu, wave, simd, data[32]; simd 634 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c simd = (*pos & GENMASK_ULL(44, 37)) >> 37; simd 642 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); simd 695 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; simd 706 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c simd = (*pos & GENMASK_ULL(51, 44)) >> 44; simd 720 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data); simd 723 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); simd 190 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, simd 192 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, simd 195 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, simd 1131 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) simd 1136 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WARN_ON(simd != 0); simd 1157 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, simd 1161 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WARN_ON(simd != 0); simd 1168 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, simd 2987 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) simd 2991 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 2997 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, simd 3003 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 3012 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) simd 3016 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); simd 3017 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); simd 3018 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); simd 3019 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); simd 3020 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); simd 3021 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); simd 3022 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); simd 3023 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); simd 3024 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); simd 3025 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); simd 3026 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); simd 3027 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); simd 3028 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); simd 3029 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); simd 3030 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); simd 3031 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); simd 3032 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); simd 3033 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); simd 3036 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, simd 3041 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c adev, simd, wave, 0, simd 4141 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) simd 4145 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 4151 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, simd 4157 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 4166 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) simd 4170 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); simd 4171 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); simd 4172 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); simd 4173 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); simd 4174 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); simd 4175 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); simd 4176 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); simd 4177 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); simd 4178 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); simd 4179 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); simd 4180 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); simd 4181 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); simd 4182 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); simd 4183 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); simd 4184 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); simd 4185 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); simd 4186 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); simd 4187 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); simd 4190 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, simd 4195 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c adev, simd, wave, 0, simd 5241 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) simd 5245 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 5251 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, simd 5257 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 5266 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) simd 5270 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); simd 5271 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); simd 5272 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); simd 5273 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); simd 5274 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); simd 5275 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); simd 5276 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); simd 5277 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); simd 5278 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); simd 5279 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); simd 5280 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); simd 5281 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); simd 5282 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO); simd 5283 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI); simd 5284 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO); simd 5285 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI); simd 5286 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); simd 5287 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); simd 5290 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, simd 5295 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev, simd, wave, 0, simd 1776 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) simd 1780 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 1786 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, simd 1792 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | simd 1801 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) simd 1805 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); simd 1806 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); simd 1807 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); simd 1808 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); simd 1809 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); simd 1810 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); simd 1811 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); simd 1812 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); simd 1813 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); simd 1814 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); simd 1815 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); simd 1816 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); simd 1817 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); simd 1818 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); simd 1821 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, simd 1826 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev, simd, wave, 0, simd 1830 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, simd 1836 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c adev, simd, wave, thread,