si_pi 1983 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 1987 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_tahiti; si_pi 1988 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->lcac_config = lcac_tahiti; si_pi 1989 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_override = cac_override_tahiti; si_pi 1990 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data = &powertune_data_tahiti; si_pi 1991 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_tahiti; si_pi 1995 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data.enable_dte_by_default = true; si_pi 1998 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_new_zealand; si_pi 2004 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_aruba_pro; si_pi 2008 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_malta; si_pi 2012 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_tahiti_pro; si_pi 2016 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->dte_data.enable_dte_by_default == true) si_pi 2021 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_pitcairn; si_pi 2022 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->lcac_config = lcac_pitcairn; si_pi 2023 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_override = cac_override_pitcairn; si_pi 2024 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data = &powertune_data_pitcairn; si_pi 2029 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_curacao_xt; si_pi 2034 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_curacao_pro; si_pi 2039 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_neptune_xt; si_pi 2043 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_pitcairn; si_pi 2047 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->lcac_config = lcac_cape_verde; si_pi 2048 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_override = cac_override_cape_verde; si_pi 2049 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data = &powertune_data_cape_verde; si_pi 2056 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_cape_verde_pro; si_pi 2057 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 2060 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_cape_verde_pro; si_pi 2061 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_sun_xt; si_pi 2066 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_heathrow; si_pi 2067 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 2071 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_chelsea_xt; si_pi 2072 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 2075 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_chelsea_pro; si_pi 2076 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 2079 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_heathrow; si_pi 2080 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_venus_xtx; si_pi 2083 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_heathrow; si_pi 2084 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_venus_xt; si_pi 2090 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_chelsea_pro; si_pi 2091 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_venus_pro; si_pi 2094 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_cape_verde; si_pi 2095 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 2099 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->lcac_config = lcac_mars_pro; si_pi 2100 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2101 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data = &powertune_data_mars_pro; si_pi 2102 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_mars_pro; si_pi 2109 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_mars_pro; si_pi 2116 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_mars_xt; si_pi 2122 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_oland_pro; si_pi 2126 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_oland_xt; si_pi 2130 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_oland; si_pi 2131 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->lcac_config = lcac_oland; si_pi 2132 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2133 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data = &powertune_data_oland; si_pi 2134 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_oland; si_pi 2138 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_weights = cac_weights_hainan; si_pi 2139 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->lcac_config = lcac_oland; si_pi 2140 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2141 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data = &powertune_data_hainan; si_pi 2142 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_data = dte_data_sun_xt; si_pi 2152 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->enable_dte = false; si_pi 2154 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->powertune_data->enable_powertune_by_default) { si_pi 2157 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->dte_data.enable_dte_by_default) { si_pi 2158 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->enable_dte = true; si_pi 2160 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_update_dte_from_pl2(adev, &si_pi->dte_data); si_pi 2171 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.l2_lta_window_size = si_pi 2172 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data->l2_lta_window_size_default; si_pi 2173 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.lts_truncate = si_pi 2174 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data->lts_truncate_default; si_pi 2177 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.l2_lta_window_size = 0; si_pi 2178 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.lts_truncate = 0; si_pi 2181 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.disable_uvd_powertune = false; si_pi 2251 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2254 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; si_pi 2283 drivers/gpu/drm/amd/amdgpu/si_dpm.c (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + si_pi 2287 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 2291 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->enable_ppm) { si_pi 2292 drivers/gpu/drm/amd/amdgpu/si_dpm.c papm_parm = &si_pi->papm_parm; si_pi 2301 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, si_pi 2304 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 2316 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2319 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; si_pi 2331 drivers/gpu/drm/amd/amdgpu/si_dpm.c (si_pi->state_table_start + si_pi 2336 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 2369 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2371 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->dyn_powertune_data.disable_uvd_powertune && si_pi 2567 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2569 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_dte_data *dte_data = &si_pi->dte_data; si_pi 2576 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->enable_dte = false; si_pi 2578 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->enable_dte == false) si_pi 2586 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->enable_dte = false; si_pi 2623 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, si_pi 2626 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 2635 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2654 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->powertune_data->lkge_lut_v0_percent > 100) si_pi 2657 drivers/gpu/drm/amd/amdgpu/si_dpm.c v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; si_pi 2681 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2698 drivers/gpu/drm/amd/amdgpu/si_dpm.c &si_pi->powertune_data->leakage_coefficients, si_pi 2701 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.cac_leakage, si_pi 2720 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2733 drivers/gpu/drm/amd/amdgpu/si_dpm.c &si_pi->powertune_data->leakage_coefficients, si_pi 2734 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data->fixed_kt, si_pi 2736 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.cac_leakage, si_pi 2754 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2770 drivers/gpu/drm/amd/amdgpu/si_dpm.c reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); si_pi 2773 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; si_pi 2774 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.dc_pwr_value = si_pi 2775 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; si_pi 2776 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); si_pi 2777 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; si_pi 2779 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; si_pi 2790 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) si_pi 2802 drivers/gpu/drm/amd/amdgpu/si_dpm.c cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); si_pi 2803 drivers/gpu/drm/amd/amdgpu/si_dpm.c cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; si_pi 2804 drivers/gpu/drm/amd/amdgpu/si_dpm.c cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; si_pi 2808 drivers/gpu/drm/amd/amdgpu/si_dpm.c cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); si_pi 2812 drivers/gpu/drm/amd/amdgpu/si_dpm.c cac_tables->cac_temp = si_pi->powertune_data->operating_temp; si_pi 2816 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, si_pi 2819 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 2879 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2886 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_program_cac_config_registers(adev, si_pi->lcac_config); si_pi 2889 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_program_cac_config_registers(adev, si_pi->cac_override); si_pi 2892 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_program_cac_config_registers(adev, si_pi->cac_weights); si_pi 2904 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2925 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->enable_dte) { si_pi 2932 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->enable_dte) si_pi 2949 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 2959 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->spll_table_start == 0) si_pi 3004 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, si_pi 3007 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 3021 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 3024 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < si_pi->leakage_voltage.count; i++){ si_pi 3025 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) si_pi 3026 drivers/gpu/drm/amd/amdgpu/si_dpm.c highest_leakage = si_pi->leakage_voltage.entries[i].voltage; si_pi 3029 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) si_pi 3646 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 3649 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start + reg_offset, value, si_pi 3650 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 3657 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 3660 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start + reg_offset, si_pi 3661 drivers/gpu/drm/amd/amdgpu/si_dpm.c value, si_pi->sram_end); si_pi 3694 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 3702 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->leakage_voltage.entries[count].voltage = vddc; si_pi 3703 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->leakage_voltage.entries[count].leakage_index = si_pi 3708 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->leakage_voltage.count = count; si_pi 3714 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 3729 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < si_pi->leakage_voltage.count; i++) { si_pi 3730 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->leakage_voltage.entries[i].leakage_index == index) { si_pi 3731 drivers/gpu/drm/amd/amdgpu/si_dpm.c *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; si_pi 3940 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 3947 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 3951 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->state_table_start = tmp; si_pi 3956 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 3960 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->soft_regs_start = tmp; si_pi 3965 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 3969 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table_start = tmp; si_pi 3974 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 3978 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_table_start = tmp; si_pi 3983 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 3987 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->arb_table_start = tmp; si_pi 3992 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 3996 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->cac_table_start = tmp; si_pi 4001 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 4005 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->dte_table_start = tmp; si_pi 4010 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 4014 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->spll_table_start = tmp; si_pi 4019 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 4023 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->papm_cfg_table_start = tmp; si_pi 4030 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4032 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); si_pi 4033 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); si_pi 4034 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); si_pi 4035 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); si_pi 4036 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); si_pi 4037 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); si_pi 4038 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); si_pi 4039 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); si_pi 4040 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); si_pi 4041 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); si_pi 4042 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); si_pi 4043 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); si_pi 4044 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); si_pi 4045 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); si_pi 4046 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); si_pi 4347 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4352 drivers/gpu/drm/amd/amdgpu/si_dpm.c return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); si_pi 4424 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4437 drivers/gpu/drm/amd/amdgpu/si_dpm.c } else if (si_pi->voltage_control_svi2) { si_pi 4458 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddci_control_svi2) { si_pi 4468 drivers/gpu/drm/amd/amdgpu/si_dpm.c VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); si_pi 4475 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->mvdd_voltage_table.count == 0) { si_pi 4480 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) si_pi 4483 drivers/gpu/drm/amd/amdgpu/si_dpm.c &si_pi->mvdd_voltage_table); si_pi 4486 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 4488 drivers/gpu/drm/amd/amdgpu/si_dpm.c VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); si_pi 4490 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = false; si_pi 4492 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((si_pi->vddc_phase_shed_table.count == 0) || si_pi 4493 drivers/gpu/drm/amd/amdgpu/si_dpm.c (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) si_pi 4494 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = false; si_pi 4515 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4518 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->voltage_control_svi2) { si_pi 4520 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->svc_gpio_id); si_pi 4522 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->svd_gpio_id); si_pi 4547 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->mvdd_voltage_table.count) { si_pi 4548 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); si_pi 4551 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); si_pi 4554 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 4555 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, si_pi 4557 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); si_pi 4560 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); si_pi 4563 drivers/gpu/drm/amd/amdgpu/si_dpm.c (u32)si_pi->vddc_phase_shed_table.phase_delay); si_pi 4565 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = false; si_pi 4597 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4603 drivers/gpu/drm/amd/amdgpu/si_dpm.c voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; si_pi 4605 drivers/gpu/drm/amd/amdgpu/si_dpm.c voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); si_pi 4692 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4696 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, si_pi 4697 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 4704 drivers/gpu/drm/amd/amdgpu/si_dpm.c return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, si_pi 4705 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp, si_pi->sram_end); si_pi 4721 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4725 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, si_pi 4726 drivers/gpu/drm/amd/amdgpu/si_dpm.c &tmp, si_pi->sram_end); si_pi 4787 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4797 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->arb_table_start + si_pi 4802 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 4821 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4824 drivers/gpu/drm/amd/amdgpu/si_dpm.c return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, si_pi 4825 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mvdd_bootup_value, voltage); si_pi 4837 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4842 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.dll_cntl); si_pi 4844 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); si_pi 4846 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); si_pi 4848 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); si_pi 4850 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); si_pi 4852 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); si_pi 4854 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); si_pi 4856 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss1); si_pi 4858 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss2); si_pi 4864 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); si_pi 4866 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); si_pi 4868 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); si_pi 4870 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); si_pi 4872 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); si_pi 4874 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); si_pi 4906 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) si_pi 4919 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; si_pi 4956 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 4957 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; si_pi 4958 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; si_pi 4959 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; si_pi 4960 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; si_pi 4961 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 dll_cntl = si_pi->clock_registers.dll_cntl; si_pi 4962 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; si_pi 4963 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; si_pi 4964 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; si_pi 4965 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; si_pi 4966 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; si_pi 4967 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; si_pi 4988 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; si_pi 4990 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 5014 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sys_pcie_mask, si_pi 5015 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->boot_pcie_gen, si_pi 5018 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) si_pi 5057 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss1); si_pi 5059 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss2); si_pi 5097 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5098 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5126 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5127 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5140 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->arb_table_start + si_pi 5145 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 5159 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5161 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5162 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; si_pi 5239 drivers/gpu/drm/amd/amdgpu/si_dpm.c return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, si_pi 5241 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 5249 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5251 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; si_pi 5252 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; si_pi 5253 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; si_pi 5254 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; si_pi 5255 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; si_pi 5256 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; si_pi 5343 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5344 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 dll_cntl = si_pi->clock_registers.dll_cntl; si_pi 5345 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; si_pi 5346 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; si_pi 5347 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; si_pi 5348 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; si_pi 5349 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; si_pi 5350 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; si_pi 5351 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; si_pi 5352 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; si_pi 5445 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5452 drivers/gpu/drm/amd/amdgpu/si_dpm.c (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID)) si_pi 5453 drivers/gpu/drm/amd/amdgpu/si_dpm.c level->gen2PCIE = (u8)si_pi->force_pcie_gen; si_pi 5530 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 5541 drivers/gpu/drm/amd/amdgpu/si_dpm.c level->MaxPoweredUpCU = si_pi->max_cu; si_pi 5599 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5600 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5612 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_power_info *si_pi = si_get_pi(adev); si_pi 5613 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5640 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_power_info *si_pi = si_get_pi(adev); si_pi 5641 drivers/gpu/drm/amd/amdgpu/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5657 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5682 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { si_pi 5734 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5737 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 address = si_pi->state_table_start + si_pi 5742 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; si_pi 5751 drivers/gpu/drm/amd/amdgpu/si_dpm.c state_size, si_pi->sram_end); si_pi 5756 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5757 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5761 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 address = si_pi->state_table_start + si_pi 5763 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; si_pi 5771 drivers/gpu/drm/amd/amdgpu/si_dpm.c state_size, si_pi->sram_end); si_pi 5989 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 5991 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; si_pi 6040 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6043 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { si_pi 6044 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->mc_reg_table.valid_flag & (1 << j)) { si_pi 6048 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); si_pi 6050 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); si_pi 6075 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6078 drivers/gpu/drm/amd/amdgpu/si_dpm.c for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { si_pi 6079 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) si_pi 6083 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) si_pi 6086 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], si_pi 6087 drivers/gpu/drm/amd/amdgpu/si_dpm.c mc_reg_table_data, si_pi->mc_reg_table.last, si_pi 6088 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.valid_flag); si_pi 6109 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6110 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 6111 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; si_pi 6122 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], si_pi 6124 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.last, si_pi 6125 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.valid_flag); si_pi 6131 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], si_pi 6133 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.last, si_pi 6134 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mc_reg_table.valid_flag); si_pi 6138 drivers/gpu/drm/amd/amdgpu/si_dpm.c return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, si_pi 6140 drivers/gpu/drm/amd/amdgpu/si_dpm.c sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); si_pi 6147 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6148 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 address = si_pi->mc_reg_table_start + si_pi 6151 drivers/gpu/drm/amd/amdgpu/si_dpm.c SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; si_pi 6160 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 6200 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6204 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID) si_pi 6207 drivers/gpu/drm/amd/amdgpu/si_dpm.c current_link_speed = si_pi->force_pcie_gen; si_pi 6209 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; si_pi 6210 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->pspp_notify_required = false; si_pi 6217 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2; si_pi 6227 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); si_pi 6232 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->pspp_notify_required = true; si_pi 6240 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6244 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->pspp_notify_required) { si_pi 6283 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6292 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->max_cu = 10; si_pi 6298 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->max_cu = 8; si_pi 6306 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->max_cu = 10; si_pi 6311 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->max_cu = 8; si_pi 6314 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->max_cu = 0; si_pi 6318 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->max_cu = 0; si_pi 6445 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6448 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->fan_ctrl_is_in_default_mode) { si_pi 6450 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_ctrl_default_mode = tmp; si_pi 6452 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->t_min = tmp; si_pi 6453 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_ctrl_is_in_default_mode = false; si_pi 6467 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6476 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (!si_pi->fan_table_start) { si_pi 6521 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_table_start, si_pi 6524 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end); si_pi 6536 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6541 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_is_controlled_by_smc = true; si_pi 6550 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6556 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_is_controlled_by_smc = false; si_pi 6593 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6601 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->fan_is_controlled_by_smc) si_pi 6644 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6647 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->fan_is_controlled_by_smc) si_pi 6708 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6711 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (!si_pi->fan_ctrl_is_in_default_mode) { si_pi 6713 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); si_pi 6717 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp |= TMIN(si_pi->t_min); si_pi 6719 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_ctrl_is_in_default_mode = true; si_pi 6785 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 6791 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pi->voltage_control || si_pi->voltage_control_svi2) si_pi 6795 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pi->voltage_control || si_pi->voltage_control_svi2) { si_pi 7138 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi = si_get_pi(adev); si_pi 7155 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sys_pcie_mask, si_pi 7156 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->boot_pcie_gen, si_pi 7168 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->acpi_pcie_gen = pl->pcie_gen; si_pi 7174 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.supported = false; si_pi 7175 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.pl = *pl; si_pi 7176 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.one_pcie_lane_in_ulv = false; si_pi 7177 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; si_pi 7178 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; si_pi 7179 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; si_pi 7196 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->mvdd_bootup_value = mvdd; si_pi 7310 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_power_info *si_pi; si_pi 7314 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); si_pi 7315 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi == NULL) si_pi 7317 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.priv = si_pi; si_pi 7318 drivers/gpu/drm/amd/amdgpu/si_dpm.c ni_pi = &si_pi->ni; si_pi 7322 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sys_pcie_mask = si_pi 7324 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; si_pi 7325 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); si_pi 7396 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->voltage_control_svi2 = si_pi 7399 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (si_pi->voltage_control_svi2) si_pi 7401 drivers/gpu/drm/amd/amdgpu/si_dpm.c &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); si_pi 7412 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddci_control_svi2 = si_pi 7416 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->vddc_phase_shed_control = si_pi 7429 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sclk_deep_sleep_above_low = false; si_pi 7446 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->sram_end = SMC_RAM_END; si_pi 7464 drivers/gpu/drm/amd/amdgpu/si_dpm.c si_pi->fan_ctrl_is_in_default_mode = true; si_pi 1871 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 1875 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_tahiti; si_pi 1876 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_tahiti; si_pi 1877 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_tahiti; si_pi 1878 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_tahiti; si_pi 1879 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_tahiti; si_pi 1883 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data.enable_dte_by_default = true; si_pi 1886 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_new_zealand; si_pi 1892 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_aruba_pro; si_pi 1896 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_malta; si_pi 1900 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_tahiti_pro; si_pi 1904 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->dte_data.enable_dte_by_default == true) si_pi 1912 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_pitcairn; si_pi 1913 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_pitcairn; si_pi 1914 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_pitcairn; si_pi 1915 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_pitcairn; si_pi 1916 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_curacao_xt; si_pi 1921 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_pitcairn; si_pi 1922 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_pitcairn; si_pi 1923 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_pitcairn; si_pi 1924 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_pitcairn; si_pi 1925 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_curacao_pro; si_pi 1930 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_pitcairn; si_pi 1931 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_pitcairn; si_pi 1932 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_pitcairn; si_pi 1933 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_pitcairn; si_pi 1934 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_neptune_xt; si_pi 1938 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_pitcairn; si_pi 1939 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_pitcairn; si_pi 1940 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_pitcairn; si_pi 1941 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_pitcairn; si_pi 1942 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_pitcairn; si_pi 1946 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_cape_verde; si_pi 1947 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_cape_verde; si_pi 1948 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_cape_verde; si_pi 1955 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_cape_verde_pro; si_pi 1956 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 1959 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_cape_verde_pro; si_pi 1960 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_sun_xt; si_pi 1965 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_heathrow; si_pi 1966 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 1970 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_chelsea_xt; si_pi 1971 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 1974 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_chelsea_pro; si_pi 1975 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 1978 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_heathrow; si_pi 1979 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_venus_xtx; si_pi 1982 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_heathrow; si_pi 1983 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_venus_xt; si_pi 1989 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_chelsea_pro; si_pi 1990 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_venus_pro; si_pi 1993 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_cape_verde; si_pi 1994 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_cape_verde; si_pi 2003 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_mars_pro; si_pi 2004 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_mars_pro; si_pi 2005 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2006 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_mars_pro; si_pi 2007 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_mars_pro; si_pi 2014 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_mars_xt; si_pi 2015 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_mars_pro; si_pi 2016 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2017 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_mars_pro; si_pi 2018 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_mars_pro; si_pi 2024 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_oland_pro; si_pi 2025 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_mars_pro; si_pi 2026 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2027 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_mars_pro; si_pi 2028 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_mars_pro; si_pi 2032 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_oland_xt; si_pi 2033 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_mars_pro; si_pi 2034 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2035 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_mars_pro; si_pi 2036 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_mars_pro; si_pi 2040 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_oland; si_pi 2041 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_oland; si_pi 2042 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2043 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_oland; si_pi 2044 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_oland; si_pi 2048 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_weights = cac_weights_hainan; si_pi 2049 drivers/gpu/drm/radeon/si_dpm.c si_pi->lcac_config = lcac_oland; si_pi 2050 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_override = cac_override_oland; si_pi 2051 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data = &powertune_data_hainan; si_pi 2052 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_data = dte_data_sun_xt; si_pi 2062 drivers/gpu/drm/radeon/si_dpm.c si_pi->enable_dte = false; si_pi 2064 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->powertune_data->enable_powertune_by_default) { si_pi 2067 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->dte_data.enable_dte_by_default) { si_pi 2068 drivers/gpu/drm/radeon/si_dpm.c si_pi->enable_dte = true; si_pi 2070 drivers/gpu/drm/radeon/si_dpm.c si_update_dte_from_pl2(rdev, &si_pi->dte_data); si_pi 2081 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.l2_lta_window_size = si_pi 2082 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data->l2_lta_window_size_default; si_pi 2083 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.lts_truncate = si_pi 2084 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data->lts_truncate_default; si_pi 2087 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.l2_lta_window_size = 0; si_pi 2088 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.lts_truncate = 0; si_pi 2091 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.disable_uvd_powertune = false; si_pi 2161 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2164 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; si_pi 2193 drivers/gpu/drm/radeon/si_dpm.c (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + si_pi 2197 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 2201 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->enable_ppm) { si_pi 2202 drivers/gpu/drm/radeon/si_dpm.c papm_parm = &si_pi->papm_parm; si_pi 2211 drivers/gpu/drm/radeon/si_dpm.c ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, si_pi 2214 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 2226 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2229 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; si_pi 2241 drivers/gpu/drm/radeon/si_dpm.c (si_pi->state_table_start + si_pi 2246 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 2279 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2281 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->dyn_powertune_data.disable_uvd_powertune && si_pi 2471 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2473 drivers/gpu/drm/radeon/si_dpm.c struct si_dte_data *dte_data = &si_pi->dte_data; si_pi 2480 drivers/gpu/drm/radeon/si_dpm.c si_pi->enable_dte = false; si_pi 2482 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->enable_dte == false) si_pi 2490 drivers/gpu/drm/radeon/si_dpm.c si_pi->enable_dte = false; si_pi 2527 drivers/gpu/drm/radeon/si_dpm.c ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, si_pi 2528 drivers/gpu/drm/radeon/si_dpm.c sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); si_pi 2537 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2557 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->powertune_data->lkge_lut_v0_percent > 100) si_pi 2560 drivers/gpu/drm/radeon/si_dpm.c v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; si_pi 2584 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2601 drivers/gpu/drm/radeon/si_dpm.c &si_pi->powertune_data->leakage_coefficients, si_pi 2604 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.cac_leakage, si_pi 2623 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2636 drivers/gpu/drm/radeon/si_dpm.c &si_pi->powertune_data->leakage_coefficients, si_pi 2637 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data->fixed_kt, si_pi 2639 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.cac_leakage, si_pi 2657 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2673 drivers/gpu/drm/radeon/si_dpm.c reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); si_pi 2676 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; si_pi 2677 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.dc_pwr_value = si_pi 2678 drivers/gpu/drm/radeon/si_dpm.c si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; si_pi 2679 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); si_pi 2680 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; si_pi 2682 drivers/gpu/drm/radeon/si_dpm.c si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; si_pi 2693 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) si_pi 2705 drivers/gpu/drm/radeon/si_dpm.c cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); si_pi 2706 drivers/gpu/drm/radeon/si_dpm.c cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; si_pi 2707 drivers/gpu/drm/radeon/si_dpm.c cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; si_pi 2711 drivers/gpu/drm/radeon/si_dpm.c cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); si_pi 2715 drivers/gpu/drm/radeon/si_dpm.c cac_tables->cac_temp = si_pi->powertune_data->operating_temp; si_pi 2719 drivers/gpu/drm/radeon/si_dpm.c ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, si_pi 2720 drivers/gpu/drm/radeon/si_dpm.c sizeof(PP_SIslands_CacConfig), si_pi->sram_end); si_pi 2780 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2787 drivers/gpu/drm/radeon/si_dpm.c ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); si_pi 2790 drivers/gpu/drm/radeon/si_dpm.c ret = si_program_cac_config_registers(rdev, si_pi->cac_override); si_pi 2793 drivers/gpu/drm/radeon/si_dpm.c ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); si_pi 2805 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2826 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->enable_dte) { si_pi 2833 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->enable_dte) si_pi 2850 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2860 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->spll_table_start == 0) si_pi 2906 drivers/gpu/drm/radeon/si_dpm.c ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, si_pi 2908 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 2922 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 2925 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < si_pi->leakage_voltage.count; i++){ si_pi 2926 drivers/gpu/drm/radeon/si_dpm.c if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) si_pi 2927 drivers/gpu/drm/radeon/si_dpm.c highest_leakage = si_pi->leakage_voltage.entries[i].voltage; si_pi 2930 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) si_pi 3187 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3190 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start + reg_offset, value, si_pi 3191 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 3198 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3201 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start + reg_offset, si_pi 3202 drivers/gpu/drm/radeon/si_dpm.c value, si_pi->sram_end); si_pi 3235 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3243 drivers/gpu/drm/radeon/si_dpm.c si_pi->leakage_voltage.entries[count].voltage = vddc; si_pi 3244 drivers/gpu/drm/radeon/si_dpm.c si_pi->leakage_voltage.entries[count].leakage_index = si_pi 3249 drivers/gpu/drm/radeon/si_dpm.c si_pi->leakage_voltage.count = count; si_pi 3255 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3270 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < si_pi->leakage_voltage.count; i++) { si_pi 3271 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->leakage_voltage.entries[i].leakage_index == index) { si_pi 3272 drivers/gpu/drm/radeon/si_dpm.c *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; si_pi 3480 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3487 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3491 drivers/gpu/drm/radeon/si_dpm.c si_pi->state_table_start = tmp; si_pi 3496 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3500 drivers/gpu/drm/radeon/si_dpm.c si_pi->soft_regs_start = tmp; si_pi 3505 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3509 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table_start = tmp; si_pi 3514 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3518 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_table_start = tmp; si_pi 3523 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3527 drivers/gpu/drm/radeon/si_dpm.c si_pi->arb_table_start = tmp; si_pi 3532 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3536 drivers/gpu/drm/radeon/si_dpm.c si_pi->cac_table_start = tmp; si_pi 3541 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3545 drivers/gpu/drm/radeon/si_dpm.c si_pi->dte_table_start = tmp; si_pi 3550 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3554 drivers/gpu/drm/radeon/si_dpm.c si_pi->spll_table_start = tmp; si_pi 3559 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 3563 drivers/gpu/drm/radeon/si_dpm.c si_pi->papm_cfg_table_start = tmp; si_pi 3570 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3572 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); si_pi 3573 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); si_pi 3574 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); si_pi 3575 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); si_pi 3576 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); si_pi 3577 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); si_pi 3578 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); si_pi 3579 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); si_pi 3580 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); si_pi 3581 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); si_pi 3582 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); si_pi 3583 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); si_pi 3584 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); si_pi 3585 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); si_pi 3586 drivers/gpu/drm/radeon/si_dpm.c si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); si_pi 3882 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3888 drivers/gpu/drm/radeon/si_dpm.c ret = si_load_smc_ucode(rdev, si_pi->sram_end); si_pi 3962 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 3975 drivers/gpu/drm/radeon/si_dpm.c } else if (si_pi->voltage_control_svi2) { si_pi 3996 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddci_control_svi2) { si_pi 4006 drivers/gpu/drm/radeon/si_dpm.c VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); si_pi 4013 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->mvdd_voltage_table.count == 0) { si_pi 4018 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) si_pi 4021 drivers/gpu/drm/radeon/si_dpm.c &si_pi->mvdd_voltage_table); si_pi 4024 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 4026 drivers/gpu/drm/radeon/si_dpm.c VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); si_pi 4028 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = false; si_pi 4030 drivers/gpu/drm/radeon/si_dpm.c if ((si_pi->vddc_phase_shed_table.count == 0) || si_pi 4031 drivers/gpu/drm/radeon/si_dpm.c (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) si_pi 4032 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = false; si_pi 4053 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4056 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->voltage_control_svi2) { si_pi 4058 drivers/gpu/drm/radeon/si_dpm.c si_pi->svc_gpio_id); si_pi 4060 drivers/gpu/drm/radeon/si_dpm.c si_pi->svd_gpio_id); si_pi 4085 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->mvdd_voltage_table.count) { si_pi 4086 drivers/gpu/drm/radeon/si_dpm.c si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); si_pi 4089 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); si_pi 4092 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 4093 drivers/gpu/drm/radeon/si_dpm.c if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, si_pi 4095 drivers/gpu/drm/radeon/si_dpm.c si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); si_pi 4098 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); si_pi 4101 drivers/gpu/drm/radeon/si_dpm.c (u32)si_pi->vddc_phase_shed_table.phase_delay); si_pi 4103 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = false; si_pi 4135 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4141 drivers/gpu/drm/radeon/si_dpm.c voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; si_pi 4143 drivers/gpu/drm/radeon/si_dpm.c voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); si_pi 4230 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4234 drivers/gpu/drm/radeon/si_dpm.c ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); si_pi 4241 drivers/gpu/drm/radeon/si_dpm.c return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); si_pi 4257 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4261 drivers/gpu/drm/radeon/si_dpm.c ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, si_pi 4262 drivers/gpu/drm/radeon/si_dpm.c &tmp, si_pi->sram_end); si_pi 4323 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4333 drivers/gpu/drm/radeon/si_dpm.c si_pi->arb_table_start + si_pi 4338 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 4357 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4360 drivers/gpu/drm/radeon/si_dpm.c return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, si_pi 4361 drivers/gpu/drm/radeon/si_dpm.c si_pi->mvdd_bootup_value, voltage); si_pi 4373 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4378 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.dll_cntl); si_pi 4380 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); si_pi 4382 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); si_pi 4384 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); si_pi 4386 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); si_pi 4388 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); si_pi 4390 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); si_pi 4392 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss1); si_pi 4394 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss2); si_pi 4400 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); si_pi 4402 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); si_pi 4404 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); si_pi 4406 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); si_pi 4408 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); si_pi 4410 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); si_pi 4442 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) si_pi 4457 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; si_pi 4494 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4495 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; si_pi 4496 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; si_pi 4497 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; si_pi 4498 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; si_pi 4499 drivers/gpu/drm/radeon/si_dpm.c u32 dll_cntl = si_pi->clock_registers.dll_cntl; si_pi 4500 drivers/gpu/drm/radeon/si_dpm.c u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; si_pi 4501 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; si_pi 4502 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; si_pi 4503 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; si_pi 4504 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; si_pi 4505 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; si_pi 4526 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; si_pi 4528 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 4551 drivers/gpu/drm/radeon/si_dpm.c si_pi->sys_pcie_mask, si_pi 4552 drivers/gpu/drm/radeon/si_dpm.c si_pi->boot_pcie_gen, si_pi 4555 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) si_pi 4594 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss1); si_pi 4596 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(si_pi->clock_registers.mpll_ss2); si_pi 4634 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4635 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 4663 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4664 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 4677 drivers/gpu/drm/radeon/si_dpm.c si_pi->arb_table_start + si_pi 4682 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 4697 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4699 drivers/gpu/drm/radeon/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; si_pi 4700 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; si_pi 4777 drivers/gpu/drm/radeon/si_dpm.c return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, si_pi 4779 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 4787 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4789 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; si_pi 4790 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; si_pi 4791 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; si_pi 4792 drivers/gpu/drm/radeon/si_dpm.c u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; si_pi 4793 drivers/gpu/drm/radeon/si_dpm.c u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; si_pi 4794 drivers/gpu/drm/radeon/si_dpm.c u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; si_pi 4881 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4882 drivers/gpu/drm/radeon/si_dpm.c u32 dll_cntl = si_pi->clock_registers.dll_cntl; si_pi 4883 drivers/gpu/drm/radeon/si_dpm.c u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; si_pi 4884 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; si_pi 4885 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; si_pi 4886 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; si_pi 4887 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; si_pi 4888 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; si_pi 4889 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; si_pi 4890 drivers/gpu/drm/radeon/si_dpm.c u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; si_pi 4983 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 4990 drivers/gpu/drm/radeon/si_dpm.c (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) si_pi 4991 drivers/gpu/drm/radeon/si_dpm.c level->gen2PCIE = (u8)si_pi->force_pcie_gen; si_pi 5068 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->vddc_phase_shed_control) { si_pi 5079 drivers/gpu/drm/radeon/si_dpm.c level->MaxPoweredUpCU = si_pi->max_cu; si_pi 5137 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5138 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5150 drivers/gpu/drm/radeon/si_dpm.c const struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5151 drivers/gpu/drm/radeon/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5178 drivers/gpu/drm/radeon/si_dpm.c const struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5179 drivers/gpu/drm/radeon/si_dpm.c const struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5195 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5220 drivers/gpu/drm/radeon/si_dpm.c if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { si_pi 5272 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5275 drivers/gpu/drm/radeon/si_dpm.c u32 address = si_pi->state_table_start + si_pi 5280 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; si_pi 5289 drivers/gpu/drm/radeon/si_dpm.c state_size, si_pi->sram_end); si_pi 5296 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5297 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5301 drivers/gpu/drm/radeon/si_dpm.c u32 address = si_pi->state_table_start + si_pi 5303 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; si_pi 5311 drivers/gpu/drm/radeon/si_dpm.c state_size, si_pi->sram_end); si_pi 5535 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5537 drivers/gpu/drm/radeon/si_dpm.c struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; si_pi 5586 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5589 drivers/gpu/drm/radeon/si_dpm.c for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { si_pi 5590 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->mc_reg_table.valid_flag & (1 << j)) { si_pi 5594 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); si_pi 5596 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); si_pi 5621 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5624 drivers/gpu/drm/radeon/si_dpm.c for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { si_pi 5625 drivers/gpu/drm/radeon/si_dpm.c if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) si_pi 5629 drivers/gpu/drm/radeon/si_dpm.c if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) si_pi 5632 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], si_pi 5633 drivers/gpu/drm/radeon/si_dpm.c mc_reg_table_data, si_pi->mc_reg_table.last, si_pi 5634 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.valid_flag); si_pi 5655 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5656 drivers/gpu/drm/radeon/si_dpm.c struct si_ulv_param *ulv = &si_pi->ulv; si_pi 5657 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; si_pi 5668 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], si_pi 5670 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.last, si_pi 5671 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.valid_flag); si_pi 5677 drivers/gpu/drm/radeon/si_dpm.c si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], si_pi 5679 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.last, si_pi 5680 drivers/gpu/drm/radeon/si_dpm.c si_pi->mc_reg_table.valid_flag); si_pi 5684 drivers/gpu/drm/radeon/si_dpm.c return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, si_pi 5686 drivers/gpu/drm/radeon/si_dpm.c sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); si_pi 5693 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5694 drivers/gpu/drm/radeon/si_dpm.c u32 address = si_pi->mc_reg_table_start + si_pi 5697 drivers/gpu/drm/radeon/si_dpm.c SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; si_pi 5707 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 5748 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5752 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) si_pi 5755 drivers/gpu/drm/radeon/si_dpm.c current_link_speed = si_pi->force_pcie_gen; si_pi 5757 drivers/gpu/drm/radeon/si_dpm.c si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; si_pi 5758 drivers/gpu/drm/radeon/si_dpm.c si_pi->pspp_notify_required = false; si_pi 5765 drivers/gpu/drm/radeon/si_dpm.c si_pi->force_pcie_gen = RADEON_PCIE_GEN2; si_pi 5775 drivers/gpu/drm/radeon/si_dpm.c si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); si_pi 5780 drivers/gpu/drm/radeon/si_dpm.c si_pi->pspp_notify_required = true; si_pi 5788 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5792 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->pspp_notify_required) { si_pi 5831 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 5840 drivers/gpu/drm/radeon/si_dpm.c si_pi->max_cu = 10; si_pi 5846 drivers/gpu/drm/radeon/si_dpm.c si_pi->max_cu = 8; si_pi 5854 drivers/gpu/drm/radeon/si_dpm.c si_pi->max_cu = 10; si_pi 5859 drivers/gpu/drm/radeon/si_dpm.c si_pi->max_cu = 8; si_pi 5862 drivers/gpu/drm/radeon/si_dpm.c si_pi->max_cu = 0; si_pi 5866 drivers/gpu/drm/radeon/si_dpm.c si_pi->max_cu = 0; si_pi 6010 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6013 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->fan_ctrl_is_in_default_mode) { si_pi 6015 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_ctrl_default_mode = tmp; si_pi 6017 drivers/gpu/drm/radeon/si_dpm.c si_pi->t_min = tmp; si_pi 6018 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_ctrl_is_in_default_mode = false; si_pi 6032 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6041 drivers/gpu/drm/radeon/si_dpm.c if (!si_pi->fan_table_start) { si_pi 6094 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_table_start, si_pi 6097 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end); si_pi 6109 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6114 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_is_controlled_by_smc = true; si_pi 6123 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6129 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_is_controlled_by_smc = false; si_pi 6164 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6172 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->fan_is_controlled_by_smc) si_pi 6212 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6215 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->fan_is_controlled_by_smc) si_pi 6276 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6279 drivers/gpu/drm/radeon/si_dpm.c if (!si_pi->fan_ctrl_is_in_default_mode) { si_pi 6281 drivers/gpu/drm/radeon/si_dpm.c tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); si_pi 6285 drivers/gpu/drm/radeon/si_dpm.c tmp |= TMIN(si_pi->t_min); si_pi 6287 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_ctrl_is_in_default_mode = true; si_pi 6353 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6359 drivers/gpu/drm/radeon/si_dpm.c if (pi->voltage_control || si_pi->voltage_control_svi2) si_pi 6363 drivers/gpu/drm/radeon/si_dpm.c if (pi->voltage_control || si_pi->voltage_control_svi2) { si_pi 6738 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi = si_get_pi(rdev); si_pi 6755 drivers/gpu/drm/radeon/si_dpm.c si_pi->sys_pcie_mask, si_pi 6756 drivers/gpu/drm/radeon/si_dpm.c si_pi->boot_pcie_gen, si_pi 6768 drivers/gpu/drm/radeon/si_dpm.c si_pi->acpi_pcie_gen = pl->pcie_gen; si_pi 6774 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.supported = false; si_pi 6775 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.pl = *pl; si_pi 6776 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.one_pcie_lane_in_ulv = false; si_pi 6777 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; si_pi 6778 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; si_pi 6779 drivers/gpu/drm/radeon/si_dpm.c si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; si_pi 6796 drivers/gpu/drm/radeon/si_dpm.c si_pi->mvdd_bootup_value = mvdd; si_pi 6905 drivers/gpu/drm/radeon/si_dpm.c struct si_power_info *si_pi; si_pi 6911 drivers/gpu/drm/radeon/si_dpm.c si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); si_pi 6912 drivers/gpu/drm/radeon/si_dpm.c if (si_pi == NULL) si_pi 6914 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.priv = si_pi; si_pi 6915 drivers/gpu/drm/radeon/si_dpm.c ni_pi = &si_pi->ni; si_pi 6922 drivers/gpu/drm/radeon/si_dpm.c si_pi->sys_pcie_mask = 0; si_pi 6925 drivers/gpu/drm/radeon/si_dpm.c si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | si_pi 6929 drivers/gpu/drm/radeon/si_dpm.c si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | si_pi 6932 drivers/gpu/drm/radeon/si_dpm.c si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; si_pi 6934 drivers/gpu/drm/radeon/si_dpm.c si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; si_pi 6935 drivers/gpu/drm/radeon/si_dpm.c si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); si_pi 7006 drivers/gpu/drm/radeon/si_dpm.c si_pi->voltage_control_svi2 = si_pi 7009 drivers/gpu/drm/radeon/si_dpm.c if (si_pi->voltage_control_svi2) si_pi 7011 drivers/gpu/drm/radeon/si_dpm.c &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); si_pi 7022 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddci_control_svi2 = si_pi 7026 drivers/gpu/drm/radeon/si_dpm.c si_pi->vddc_phase_shed_control = si_pi 7039 drivers/gpu/drm/radeon/si_dpm.c si_pi->sclk_deep_sleep_above_low = false; si_pi 7056 drivers/gpu/drm/radeon/si_dpm.c si_pi->sram_end = SMC_RAM_END; si_pi 7074 drivers/gpu/drm/radeon/si_dpm.c si_pi->fan_ctrl_is_in_default_mode = true;