shim 17085 drivers/gpu/drm/i915/display/intel_display.c if (connector->hdcp.shim) { shim 341 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_hdcp_shim *shim; shim 41 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim, u8 *bksv) shim 47 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_bksv(intel_dig_port, bksv); shim 65 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = connector->hdcp.shim; shim 69 drivers/gpu/drm/i915/display/intel_hdcp.c if (!shim) shim 72 drivers/gpu/drm/i915/display/intel_hdcp.c if (shim->hdcp_capable) { shim 73 drivers/gpu/drm/i915/display/intel_hdcp.c shim->hdcp_capable(intel_dig_port, &capable); shim 75 drivers/gpu/drm/i915/display/intel_hdcp.c if (!intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv)) shim 103 drivers/gpu/drm/i915/display/intel_hdcp.c hdcp->shim->hdcp_2_2_capable(intel_dig_port, &capable); shim 129 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim) shim 135 drivers/gpu/drm/i915/display/intel_hdcp.c ret = __wait_for(read_ret = shim->read_ksv_ready(intel_dig_port, shim 279 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim, shim 290 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); shim 496 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = connector->hdcp.shim; shim 501 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); shim 507 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_bstatus(intel_dig_port, bstatus); shim 536 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_ksv_fifo(intel_dig_port, num_downstream, ksv_fifo); shim 551 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_hdcp_validate_v_prime(intel_dig_port, shim, shim 577 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = hdcp->shim; shim 584 drivers/gpu/drm/i915/display/intel_hdcp.c u8 shim[DRM_HDCP_AN_LEN]; shim 588 drivers/gpu/drm/i915/display/intel_hdcp.c u8 shim[DRM_HDCP_KSV_LEN]; shim 592 drivers/gpu/drm/i915/display/intel_hdcp.c u8 shim[DRM_HDCP_RI_LEN]; shim 606 drivers/gpu/drm/i915/display/intel_hdcp.c if (shim->hdcp_capable) { shim 607 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->hdcp_capable(intel_dig_port, &hdcp_capable); shim 630 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->write_an_aksv(intel_dig_port, an.shim); shim 638 drivers/gpu/drm/i915/display/intel_hdcp.c ret = intel_hdcp_read_valid_bksv(intel_dig_port, shim, bksv.shim); shim 642 drivers/gpu/drm/i915/display/intel_hdcp.c if (drm_hdcp_check_ksvs_revoked(dev, bksv.shim, 1)) { shim 650 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->repeater_present(intel_dig_port, &repeater_present); shim 657 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->toggle_signalling(intel_dig_port, true); shim 689 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_ri_prime(intel_dig_port, ri.shim); shim 745 drivers/gpu/drm/i915/display/intel_hdcp.c ret = hdcp->shim->toggle_signalling(intel_dig_port, false); shim 832 drivers/gpu/drm/i915/display/intel_hdcp.c if (hdcp->shim->check_link(intel_dig_port)) { shim 1187 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = hdcp->shim; shim 1199 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->write_2_2_msg(intel_dig_port, &msgs.ake_init, shim 1204 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_CERT, shim 1232 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->write_2_2_msg(intel_dig_port, &msgs.no_stored_km, size); shim 1236 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_AKE_SEND_HPRIME, shim 1247 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_2_2_msg(intel_dig_port, shim 1271 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = hdcp->shim; shim 1279 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->write_2_2_msg(intel_dig_port, &msgs.lc_init, shim 1284 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_2_2_msg(intel_dig_port, shim 1310 drivers/gpu/drm/i915/display/intel_hdcp.c ret = hdcp->shim->write_2_2_msg(intel_dig_port, &send_eks, shim 1327 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = hdcp->shim; shim 1342 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->write_2_2_msg(intel_dig_port, &msgs.stream_manage, shim 1347 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_STREAM_READY, shim 1379 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = hdcp->shim; shim 1384 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->read_2_2_msg(intel_dig_port, HDCP_2_2_REP_SEND_RECVID_LIST, shim 1422 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->write_2_2_msg(intel_dig_port, &msgs.rep_ack, shim 1445 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim = hdcp->shim; shim 1466 drivers/gpu/drm/i915/display/intel_hdcp.c if (shim->config_stream_type) { shim 1467 drivers/gpu/drm/i915/display/intel_hdcp.c ret = shim->config_stream_type(intel_dig_port, shim 1500 drivers/gpu/drm/i915/display/intel_hdcp.c if (hdcp->shim->toggle_signalling) { shim 1501 drivers/gpu/drm/i915/display/intel_hdcp.c ret = hdcp->shim->toggle_signalling(intel_dig_port, true); shim 1542 drivers/gpu/drm/i915/display/intel_hdcp.c if (hdcp->shim->toggle_signalling) { shim 1543 drivers/gpu/drm/i915/display/intel_hdcp.c ret = hdcp->shim->toggle_signalling(intel_dig_port, false); shim 1655 drivers/gpu/drm/i915/display/intel_hdcp.c ret = hdcp->shim->check_2_2_link(intel_dig_port); shim 1753 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim) shim 1760 drivers/gpu/drm/i915/display/intel_hdcp.c data->protocol = (u8)shim->protocol; shim 1811 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim) shim 1816 drivers/gpu/drm/i915/display/intel_hdcp.c ret = initialize_hdcp_port_data(connector, shim); shim 1826 drivers/gpu/drm/i915/display/intel_hdcp.c const struct intel_hdcp_shim *shim) shim 1832 drivers/gpu/drm/i915/display/intel_hdcp.c if (!shim) shim 1836 drivers/gpu/drm/i915/display/intel_hdcp.c intel_hdcp2_init(connector, shim); shim 1847 drivers/gpu/drm/i915/display/intel_hdcp.c hdcp->shim = shim; shim 1862 drivers/gpu/drm/i915/display/intel_hdcp.c if (!hdcp->shim) shim 1903 drivers/gpu/drm/i915/display/intel_hdcp.c if (!hdcp->shim) shim 1937 drivers/gpu/drm/i915/display/intel_hdcp.c if (!connector->hdcp.shim) shim 1986 drivers/gpu/drm/i915/display/intel_hdcp.c if (!hdcp->shim) shim 1498 drivers/gpu/drm/i915/display/intel_hdmi.c u8 shim[DRM_HDCP_RI_LEN]; shim 1501 drivers/gpu/drm/i915/display/intel_hdmi.c ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); shim 2519 drivers/gpu/drm/i915/i915_debugfs.c if (intel_connector->hdcp.shim) { shim 2546 drivers/gpu/drm/i915/i915_debugfs.c if (intel_connector->hdcp.shim) { shim 4477 drivers/gpu/drm/i915/i915_debugfs.c if (!intel_connector->hdcp.shim) shim 195 drivers/soundwire/intel.c void __iomem *s = sdw->res->shim; shim 291 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 296 drivers/soundwire/intel.c link_control = intel_readl(shim, SDW_SHIM_LCTL); shim 301 drivers/soundwire/intel.c ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask); shim 311 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 318 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 321 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 324 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 327 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 330 drivers/soundwire/intel.c ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id)); shim 333 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 336 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 339 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 344 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl); shim 349 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act); shim 352 drivers/soundwire/intel.c sync_reg = intel_readl(shim, SDW_SHIM_SYNC); shim 358 drivers/soundwire/intel.c ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, shim 372 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 377 drivers/soundwire/intel.c pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id)); shim 390 drivers/soundwire/intel.c pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); shim 406 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 411 drivers/soundwire/intel.c count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num)); shim 423 drivers/soundwire/intel.c count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id)); shim 478 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 504 drivers/soundwire/intel.c intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf); shim 553 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 561 drivers/soundwire/intel.c sync_reg = intel_readl(shim, SDW_SHIM_SYNC); shim 563 drivers/soundwire/intel.c intel_writel(shim, SDW_SHIM_SYNC, sync_reg); shim 572 drivers/soundwire/intel.c void __iomem *shim = sdw->res->shim; shim 580 drivers/soundwire/intel.c sync_reg = intel_readl(shim, SDW_SHIM_SYNC); shim 600 drivers/soundwire/intel.c ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg, shim 20 drivers/soundwire/intel.h void __iomem *shim; shim 128 drivers/soundwire/intel_init.c link->res.shim = res->mmio_base + SDW_SHIM_BASE; shim 56 sound/soc/intel/atom/sst/sst.c isr.full = sst_shim_read64(drv->shim, SST_ISRX); shim 61 sound/soc/intel/atom/sst/sst.c header.full = sst_shim_read64(drv->shim, shim 64 sound/soc/intel/atom/sst/sst.c sst_shim_write64(drv->shim, drv->ipc_reg.ipcx, header.full); shim 68 sound/soc/intel/atom/sst/sst.c sst_shim_write64(drv->shim, SST_ISRX, isr.full); shim 79 sound/soc/intel/atom/sst/sst.c imr.full = sst_shim_read64(drv->shim, SST_IMRX); shim 81 sound/soc/intel/atom/sst/sst.c sst_shim_write64(drv->shim, SST_IMRX, imr.full); shim 83 sound/soc/intel/atom/sst/sst.c header.full = sst_shim_read64(drv->shim, drv->ipc_reg.ipcd); shim 319 sound/soc/intel/atom/sst/sst.c sst_shim_write64(ctx->shim, SST_IMRX, 0xFFFF0038); shim 356 sound/soc/intel/atom/sst/sst.h void __iomem *shim; shim 187 sound/soc/intel/atom/sst/sst_acpi.c ctx->shim = devm_ioremap_nocache(ctx->dev, ctx->shim_phy_add, shim 189 sound/soc/intel/atom/sst/sst_acpi.c if (!ctx->shim) { shim 127 sound/soc/intel/atom/sst/sst_ipc.c header.full = sst_shim_read64(sst_drv_ctx->shim, SST_IPCX); shim 138 sound/soc/intel/atom/sst/sst_ipc.c header.full = sst_shim_read64(sst_drv_ctx->shim, SST_IPCX); shim 170 sound/soc/intel/atom/sst/sst_ipc.c sst_shim_write64(sst_drv_ctx->shim, SST_IPCX, msg->mrfld_header.full); shim 187 sound/soc/intel/atom/sst/sst_ipc.c imr.full = sst_shim_read64(sst_drv_ctx->shim, SST_IMRX); shim 188 sound/soc/intel/atom/sst/sst_ipc.c isr.full = sst_shim_read64(sst_drv_ctx->shim, SST_ISRX); shim 192 sound/soc/intel/atom/sst/sst_ipc.c sst_shim_write64(sst_drv_ctx->shim, SST_ISRX, isr.full); shim 195 sound/soc/intel/atom/sst/sst_ipc.c clear_ipc.full = sst_shim_read64(sst_drv_ctx->shim, SST_IPCD); shim 200 sound/soc/intel/atom/sst/sst_ipc.c sst_shim_write64(sst_drv_ctx->shim, SST_IPCD, clear_ipc.full); shim 203 sound/soc/intel/atom/sst/sst_ipc.c sst_shim_write64(sst_drv_ctx->shim, SST_IMRX, imr.full); shim 60 sound/soc/intel/atom/sst/sst_loader.c csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); shim 65 sound/soc/intel/atom/sst/sst_loader.c sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); shim 66 sound/soc/intel/atom/sst/sst_loader.c csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); shim 71 sound/soc/intel/atom/sst/sst_loader.c sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); shim 73 sound/soc/intel/atom/sst/sst_loader.c csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); shim 88 sound/soc/intel/atom/sst/sst_loader.c csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); shim 92 sound/soc/intel/atom/sst/sst_loader.c sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); shim 94 sound/soc/intel/atom/sst/sst_loader.c csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); shim 99 sound/soc/intel/atom/sst/sst_loader.c sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); shim 101 sound/soc/intel/atom/sst/sst_loader.c csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); shim 65 sound/soc/intel/atom/sst/sst_pci.c ctx->shim = pcim_iomap(pci, 1, pci_resource_len(pci, 1)); shim 66 sound/soc/intel/atom/sst/sst_pci.c if (!ctx->shim) { shim 70 sound/soc/intel/atom/sst/sst_pci.c dev_dbg(ctx->dev, "SST Shim Ptr %p\n", ctx->shim); shim 273 sound/soc/intel/baytrail/sst-baytrail-dsp.c sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset; shim 76 sound/soc/intel/common/sst-dsp-priv.h void __iomem *shim; shim 88 sound/soc/intel/common/sst-dsp.c sst->ops->write(sst->addr.shim, offset, value); shim 99 sound/soc/intel/common/sst-dsp.c val = sst->ops->read(sst->addr.shim, offset); shim 111 sound/soc/intel/common/sst-dsp.c sst->ops->write64(sst->addr.shim, offset, value); shim 122 sound/soc/intel/common/sst-dsp.c val = sst->ops->read64(sst->addr.shim, offset); shim 131 sound/soc/intel/common/sst-dsp.c sst->ops->write(sst->addr.shim, offset, value); shim 137 sound/soc/intel/common/sst-dsp.c return sst->ops->read(sst->addr.shim, offset); shim 143 sound/soc/intel/common/sst-dsp.c sst->ops->write64(sst->addr.shim, offset, value); shim 149 sound/soc/intel/common/sst-dsp.c return sst->ops->read64(sst->addr.shim, offset); shim 478 sound/soc/intel/haswell/sst-haswell-dsp.c sst->addr.shim = sst->addr.lpe + sst->addr.shim_offset; shim 567 sound/soc/intel/skylake/bxt-sst.c sst->addr.shim = mmio_base; shim 433 sound/soc/intel/skylake/cnl-sst.c sst->addr.shim = mmio_base; shim 536 sound/soc/intel/skylake/skl-sst.c sst->addr.shim = mmio_base;