shifts 46 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c aud->shifts->field_name, aud->masks->field_name shifts 939 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c const struct dce_audio_shift *shifts, shifts 955 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c audio->shifts = shifts; shifts 127 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h const struct dce_audio_shift *shifts; shifts 135 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h const struct dce_audio_shift *shifts, shifts 38 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c hws->shifts->field_name, hws->masks->field_name shifts 41 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name shifts 620 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_shift *shifts, shifts 627 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c dce_i2c_hw->shifts = shifts; shifts 644 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_shift *shifts, shifts 654 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c shifts, shifts 679 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_shift *shifts, shifts 686 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c shifts, shifts 696 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_shift *shifts, shifts 703 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c shifts, shifts 714 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c const struct dce_i2c_shift *shifts, shifts 721 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c shifts, shifts 279 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_shift *shifts; shifts 288 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_shift *shifts, shifts 296 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_shift *shifts, shifts 304 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_shift *shifts, shifts 312 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_shift *shifts, shifts 321 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h const struct dce_i2c_shift *shifts, shifts 37 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->shifts->field_name, dce_mi->masks->field_name shifts 782 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c dce_mi->shifts = mi_shift; shifts 334 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h const struct dce_mem_input_shift *shifts; shifts 473 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c hws->shifts = &hwseq_shift; shifts 83 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c hws->shifts->field_name, hws->masks->field_name shifts 520 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c hws->shifts = &hwseq_shift; shifts 493 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c hws->shifts = &hwseq_shift; shifts 47 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c hws->shifts->field_name, hws->masks->field_name shifts 740 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c hws->shifts = &hwseq_shift; shifts 754 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c hws->shifts = &dce121_hwseq_shift; shifts 585 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c hws->shifts = &hwseq_shift; shifts 39 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c reg->shifts.field_name, reg->masks.field_name shifts 70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h struct xfer_func_shift shifts; shifts 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.h struct cm_color_matrix_shift shifts; shifts 138 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; shifts 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; shifts 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; shifts 235 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; shifts 280 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; shifts 282 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; shifts 284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; shifts 286 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; shifts 289 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; shifts 291 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; shifts 293 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B; shifts 295 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; shifts 297 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B; shifts 299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; shifts 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; shifts 309 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; shifts 311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; shifts 313 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; shifts 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B; shifts 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; shifts 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B; shifts 322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; shifts 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B; shifts 326 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; shifts 487 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11; shifts 489 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12; shifts 42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name shifts 965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c hubbub1->shifts = hubbub_shift; shifts 304 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h const struct dcn_hubbub_shift *shifts; shifts 65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c hws->shifts->field_name, hws->masks->field_name shifts 845 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c hws->shifts = &hwseq_shift; shifts 210 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; shifts 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; shifts 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; shifts 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; shifts 219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; shifts 221 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; shifts 223 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; shifts 225 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; shifts 227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; shifts 229 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; shifts 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name shifts 49 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name shifts 617 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c hubbub->shifts = hubbub_shift; shifts 79 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h const struct dcn_hubbub_shift *shifts; shifts 65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c hws->shifts->field_name, hws->masks->field_name shifts 148 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; shifts 150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; shifts 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A; shifts 190 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A; shifts 214 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region0_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; shifts 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region0_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; shifts 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region1_lut_offset = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; shifts 220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region1_num_segments = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; shifts 222 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_B; shifts 224 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; shifts 226 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_end_base = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; shifts 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.field_region_linear_slope = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; shifts 230 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_region_start = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_B; shifts 232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c reg->shifts.exp_resion_start_segment = mpc20->mpc_shift->MPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; shifts 1111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c vmid->shifts = &vmid_shifts; shifts 1253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c hws->shifts = &hwseq_shift; shifts 39 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c vmid->shifts->field_name, vmid->masks->field_name shifts 84 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h const struct dcn20_vmid_shift *shifts; shifts 40 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name shifts 50 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub1->shifts->field_name, hubbub1->masks->field_name shifts 601 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c hubbub->shifts = hubbub_shift; shifts 1185 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c vmid->shifts = &vmid_shifts; shifts 1403 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c hws->shifts = &hwseq_shift; shifts 136 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c ddc->shifts = &ddc_shift; shifts 146 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c hpd->shifts = &hpd_shift; shifts 149 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c ddc->shifts = &ddc_shift; shifts 159 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c hpd->shifts = &hpd_shift; shifts 136 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c ddc->shifts = &ddc_shift; shifts 146 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c hpd->shifts = &hpd_shift; shifts 156 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c generic->shifts = &generic_shift[en]; shifts 181 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c ddc->shifts = &ddc_shift; shifts 191 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c hpd->shifts = &hpd_shift; shifts 188 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c ddc->shifts = &ddc_shift[en]; shifts 198 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c hpd->shifts = &hpd_shift; shifts 208 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c generic->shifts = &generic_shift[en]; shifts 165 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c generic->shifts = &generic_shift[en]; shifts 190 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c ddc->shifts = &ddc_shift[en]; shifts 200 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c hpd->shifts = &hpd_shift; shifts 42 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c ddc->shifts->field_name, ddc->masks->field_name shifts 34 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.h const struct ddc_sh_mask *shifts; shifts 40 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c generic->shifts->field_name, generic->masks->field_name shifts 35 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.h const struct generic_sh_mask *shifts; shifts 40 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c hpd->shifts->field_name, hpd->masks->field_name shifts 34 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.h const struct hpd_sh_mask *shifts; shifts 61 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h const struct dce_hwseq_shift *shifts; shifts 1037 drivers/gpu/drm/omapdrm/dss/dispc.c static const unsigned int shifts[] = { 0, 8, 16, 24, }; shifts 1043 drivers/gpu/drm/omapdrm/dss/dispc.c shift = shifts[plane]; shifts 1253 drivers/gpu/drm/omapdrm/dss/dispc.c static const unsigned int shifts[] = { 6, 14, 14, 14, 14, }; shifts 1256 drivers/gpu/drm/omapdrm/dss/dispc.c shift = shifts[plane]; shifts 1349 drivers/gpu/drm/omapdrm/dss/dispc.c static const unsigned int shifts[] = { 5, 10, 10, 10 }; shifts 1355 drivers/gpu/drm/omapdrm/dss/dispc.c shift = shifts[plane]; shifts 3180 drivers/gpu/drm/omapdrm/dss/dispc.c const int shifts[] = { shifts 3191 drivers/gpu/drm/omapdrm/dss/dispc.c mask <<= 16 + shifts[channel]; shifts 3192 drivers/gpu/drm/omapdrm/dss/dispc.c val <<= 16 + shifts[channel]; shifts 816 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static const unsigned shifts[] = { 0, 8, 16, 24, }; shifts 822 drivers/video/fbdev/omap2/omapfb/dss/dispc.c shift = shifts[plane]; shifts 1041 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; shifts 1044 drivers/video/fbdev/omap2/omapfb/dss/dispc.c shift = shifts[plane]; shifts 1123 drivers/video/fbdev/omap2/omapfb/dss/dispc.c static const unsigned shifts[] = { 5, 10, 10, 10 }; shifts 1129 drivers/video/fbdev/omap2/omapfb/dss/dispc.c shift = shifts[plane]; shifts 3225 drivers/video/fbdev/omap2/omapfb/dss/dispc.c const int shifts[] = { shifts 3236 drivers/video/fbdev/omap2/omapfb/dss/dispc.c mask <<= 16 + shifts[channel]; shifts 3237 drivers/video/fbdev/omap2/omapfb/dss/dispc.c val <<= 16 + shifts[channel];