shift1 74 drivers/clk/mvebu/armada-37xx-periph.c u8 shift1; shift1 151 drivers/clk/mvebu/armada-37xx-periph.c .shift1 = _shift1, \ shift1 340 drivers/clk/mvebu/armada-37xx-periph.c div = get_div(double_div->reg1, double_div->shift1); shift1 59 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, shift1 67 drivers/gpu/drm/amd/display/dc/dc_helper.c field_value1, mask1, shift1); shift1 82 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, shift1 91 drivers/gpu/drm/amd/display/dc/dc_helper.c set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, shift1 105 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, shift1 113 drivers/gpu/drm/amd/display/dc/dc_helper.c set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, shift1 152 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 156 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 162 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 167 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 174 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 180 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 188 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 195 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 204 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 212 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 222 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 231 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 242 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 252 drivers/gpu/drm/amd/display/dc/dc_helper.c *field_value1 = get_reg_field_value_ex(reg_val, mask1, shift1); shift1 359 drivers/gpu/drm/amd/display/dc/dc_helper.c uint8_t shift1, uint32_t mask1, uint32_t field_value1, shift1 369 drivers/gpu/drm/amd/display/dc/dc_helper.c reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); shift1 136 drivers/gpu/drm/amd/display/dc/dm_services.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); shift1 140 drivers/gpu/drm/amd/display/dc/dm_services.h uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...); shift1 395 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 399 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 404 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 410 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 417 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 425 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 434 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t *field_value1, shift1 485 drivers/gpu/drm/amd/display/dc/inc/reg_helper.h uint8_t shift1, uint32_t mask1, uint32_t field_value1,