shared_timings 125 drivers/gpu/drm/msm/dsi/dsi_manager.c struct msm_dsi_phy_shared_timings *shared_timings) shared_timings 134 drivers/gpu/drm/msm/dsi/dsi_manager.c msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings); shared_timings 141 drivers/gpu/drm/msm/dsi/dsi_manager.c struct msm_dsi_phy_shared_timings shared_timings[DSI_MAX]) shared_timings 160 drivers/gpu/drm/msm/dsi/dsi_manager.c &shared_timings[DSI_CLOCK_MASTER]); shared_timings 164 drivers/gpu/drm/msm/dsi/dsi_manager.c &shared_timings[DSI_CLOCK_SLAVE]); shared_timings 172 drivers/gpu/drm/msm/dsi/dsi_manager.c ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]); shared_timings 112 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0, shared_timings 121 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = temp >> 1; shared_timings 122 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = true; shared_timings 124 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = shared_timings 126 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = false; shared_timings 134 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre, timing->shared_timings.clk_post, shared_timings 135 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, shared_timings 225 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_post = shared_timings 236 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = temp >> 1; shared_timings 237 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 1; shared_timings 239 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = shared_timings 241 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 0; shared_timings 249 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre, timing->shared_timings.clk_post, shared_timings 250 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, shared_timings 334 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_post = shared_timings 345 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = temp >> 1; shared_timings 346 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 1; shared_timings 348 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre = shared_timings 350 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2 = 0; shared_timings 358 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre, timing->shared_timings.clk_post, shared_timings 359 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, shared_timings 734 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c struct msm_dsi_phy_shared_timings *shared_timings) shared_timings 736 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c memcpy(shared_timings, &phy->timing.shared_timings, shared_timings 737 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c sizeof(*shared_timings)); shared_timings 65 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h struct msm_dsi_phy_shared_timings shared_timings;