shared_dpll       596 drivers/gpu/drm/i915/display/icl_dsi.c 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll      1022 drivers/gpu/drm/i915/display/intel_ddi.c 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll      1102 drivers/gpu/drm/i915/display/intel_ddi.c 	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
shared_dpll      1498 drivers/gpu/drm/i915/display/intel_ddi.c 						pipe_config->shared_dpll);
shared_dpll      1614 drivers/gpu/drm/i915/display/intel_ddi.c 	val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
shared_dpll      2793 drivers/gpu/drm/i915/display/intel_ddi.c 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll      2925 drivers/gpu/drm/i915/display/intel_ddi.c 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll      1629 drivers/gpu/drm/i915/display/intel_display.c 	assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
shared_dpll      5242 drivers/gpu/drm/i915/display/intel_display.c 		if (crtc_state->shared_dpll ==
shared_dpll      6454 drivers/gpu/drm/i915/display/intel_display.c 	if (pipe_config->shared_dpll)
shared_dpll      6816 drivers/gpu/drm/i915/display/intel_display.c 	if (crtc_state->shared_dpll)
shared_dpll      8782 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = NULL;
shared_dpll      9959 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = NULL;
shared_dpll      10020 drivers/gpu/drm/i915/display/intel_display.c 		pipe_config->shared_dpll =
shared_dpll      10022 drivers/gpu/drm/i915/display/intel_display.c 		pll = pipe_config->shared_dpll;
shared_dpll      10084 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
shared_dpll      10145 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
shared_dpll      10161 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
shared_dpll      10197 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
shared_dpll      10377 drivers/gpu/drm/i915/display/intel_display.c 	pll = pipe_config->shared_dpll;
shared_dpll      10419 drivers/gpu/drm/i915/display/intel_display.c 	pipe_config->shared_dpll = NULL;
shared_dpll      11783 drivers/gpu/drm/i915/display/intel_display.c 	    !WARN_ON(pipe_config->shared_dpll)) {
shared_dpll      12255 drivers/gpu/drm/i915/display/intel_display.c 	saved_state->shared_dpll = crtc_state->shared_dpll;
shared_dpll      12794 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_P(shared_dpll);
shared_dpll      13229 drivers/gpu/drm/i915/display/intel_display.c 	if (new_crtc_state->shared_dpll)
shared_dpll      13230 drivers/gpu/drm/i915/display/intel_display.c 		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
shared_dpll      13232 drivers/gpu/drm/i915/display/intel_display.c 	if (old_crtc_state->shared_dpll &&
shared_dpll      13233 drivers/gpu/drm/i915/display/intel_display.c 	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
shared_dpll      13235 drivers/gpu/drm/i915/display/intel_display.c 		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
shared_dpll      16523 drivers/gpu/drm/i915/display/intel_display.c 		crtc_state->shared_dpll &&
shared_dpll      16714 drivers/gpu/drm/i915/display/intel_display.c 			    crtc_state->shared_dpll == pll)
shared_dpll       492 drivers/gpu/drm/i915/display/intel_display_types.h 	struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
shared_dpll       840 drivers/gpu/drm/i915/display/intel_display_types.h 	struct intel_shared_dpll *shared_dpll;
shared_dpll        50 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 				  struct intel_shared_dpll_state *shared_dpll)
shared_dpll        58 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		shared_dpll[i] = pll->state;
shared_dpll        73 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 						  state->shared_dpll);
shared_dpll        76 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	return state->shared_dpll;
shared_dpll       141 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll       168 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll       213 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
shared_dpll       255 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll_state *shared_dpll;
shared_dpll       258 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
shared_dpll       264 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		if (shared_dpll[i].crtc_mask == 0) {
shared_dpll       271 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 			   &shared_dpll[i].hw_state,
shared_dpll       276 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 				      shared_dpll[i].crtc_mask,
shared_dpll       299 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll_state *shared_dpll;
shared_dpll       302 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
shared_dpll       304 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (shared_dpll[id].crtc_mask == 0)
shared_dpll       305 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		shared_dpll[id].hw_state = *pll_state;
shared_dpll       310 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	shared_dpll[id].crtc_mask |= 1 << crtc->pipe;
shared_dpll       317 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll_state *shared_dpll;
shared_dpll       319 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
shared_dpll       320 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	shared_dpll[pll->info->id].crtc_mask &= ~(1 << crtc->pipe);
shared_dpll       331 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	new_crtc_state->shared_dpll = NULL;
shared_dpll       333 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	if (!old_crtc_state->shared_dpll)
shared_dpll       336 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
shared_dpll       353 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
shared_dpll       363 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		swap(pll->state, shared_dpll[i]);
shared_dpll       478 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->shared_dpll = pll;
shared_dpll       906 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->shared_dpll = pll;
shared_dpll      1478 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->shared_dpll = pll;
shared_dpll      1914 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->shared_dpll = pll;
shared_dpll      2429 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->shared_dpll = pll;
shared_dpll      2876 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	crtc_state->shared_dpll = port_dpll->pll;
shared_dpll      3025 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	new_crtc_state->shared_dpll = NULL;
shared_dpll       241 drivers/gpu/drm/i915/display/intel_lvds.c 					    pipe_config->shared_dpll);