shadow_ring_context 62 drivers/gpu/drm/i915/gvt/scheduler.c struct execlist_ring_context *shadow_ring_context; shadow_ring_context 72 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context = kmap(page); shadow_ring_context 73 drivers/gpu/drm/i915/gvt/scheduler.c set_context_pdp_root_pointer(shadow_ring_context, shadow_ring_context 133 drivers/gpu/drm/i915/gvt/scheduler.c struct execlist_ring_context *shadow_ring_context; shadow_ring_context 140 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context = kmap(page); shadow_ring_context 142 drivers/gpu/drm/i915/gvt/scheduler.c sr_oa_regs(workload, (u32 *)shadow_ring_context, true); shadow_ring_context 145 drivers/gpu/drm/i915/gvt/scheduler.c + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) shadow_ring_context 149 drivers/gpu/drm/i915/gvt/scheduler.c &shadow_ring_context->name.val, 4);\ shadow_ring_context 150 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context->name.val |= 0xffff << 16;\ shadow_ring_context 166 drivers/gpu/drm/i915/gvt/scheduler.c sizeof(*shadow_ring_context), shadow_ring_context 167 drivers/gpu/drm/i915/gvt/scheduler.c (void *)shadow_ring_context + shadow_ring_context 168 drivers/gpu/drm/i915/gvt/scheduler.c sizeof(*shadow_ring_context), shadow_ring_context 169 drivers/gpu/drm/i915/gvt/scheduler.c I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context)); shadow_ring_context 171 drivers/gpu/drm/i915/gvt/scheduler.c sr_oa_regs(workload, (u32 *)shadow_ring_context, false); shadow_ring_context 174 drivers/gpu/drm/i915/gvt/scheduler.c if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val)) shadow_ring_context 535 drivers/gpu/drm/i915/gvt/scheduler.c struct execlist_ring_context *shadow_ring_context = shadow_ring_context 538 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context->bb_per_ctx_ptr.val = shadow_ring_context 539 drivers/gpu/drm/i915/gvt/scheduler.c (shadow_ring_context->bb_per_ctx_ptr.val & shadow_ring_context 541 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context->rcs_indirect_ctx.val = shadow_ring_context 542 drivers/gpu/drm/i915/gvt/scheduler.c (shadow_ring_context->rcs_indirect_ctx.val & shadow_ring_context 804 drivers/gpu/drm/i915/gvt/scheduler.c struct execlist_ring_context *shadow_ring_context; shadow_ring_context 863 drivers/gpu/drm/i915/gvt/scheduler.c shadow_ring_context = kmap(page); shadow_ring_context 867 drivers/gpu/drm/i915/gvt/scheduler.c RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4) shadow_ring_context 876 drivers/gpu/drm/i915/gvt/scheduler.c sizeof(*shadow_ring_context), shadow_ring_context 877 drivers/gpu/drm/i915/gvt/scheduler.c (void *)shadow_ring_context + shadow_ring_context 878 drivers/gpu/drm/i915/gvt/scheduler.c sizeof(*shadow_ring_context), shadow_ring_context 879 drivers/gpu/drm/i915/gvt/scheduler.c I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));