sh_per_se        1377 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
sh_per_se        1379 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
sh_per_se        1390 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
sh_per_se        1674 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
sh_per_se        1676 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
sh_per_se        1687 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
sh_per_se        3538 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
sh_per_se        3540 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
sh_per_se        3551 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
sh_per_se        3087 drivers/gpu/drm/radeon/cik.c 			      u32 sh_per_se)
sh_per_se        3100 drivers/gpu/drm/radeon/cik.c 	mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
sh_per_se        3116 drivers/gpu/drm/radeon/cik.c 			 u32 se_num, u32 sh_per_se,
sh_per_se        3125 drivers/gpu/drm/radeon/cik.c 		for (j = 0; j < sh_per_se; j++) {
sh_per_se        3127 drivers/gpu/drm/radeon/cik.c 			data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
sh_per_se        3129 drivers/gpu/drm/radeon/cik.c 				disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
sh_per_se        3131 drivers/gpu/drm/radeon/cik.c 				disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
sh_per_se        3148 drivers/gpu/drm/radeon/cik.c 		for (j = 0; j < sh_per_se; j++) {
sh_per_se        3157 drivers/gpu/drm/radeon/cik.c 				data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
sh_per_se        3160 drivers/gpu/drm/radeon/cik.c 				data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
sh_per_se        3164 drivers/gpu/drm/radeon/cik.c 				data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
sh_per_se        2997 drivers/gpu/drm/radeon/si.c 			 u32 se_num, u32 sh_per_se,
sh_per_se        3004 drivers/gpu/drm/radeon/si.c 		for (j = 0; j < sh_per_se; j++) {
sh_per_se        3025 drivers/gpu/drm/radeon/si.c 			      u32 sh_per_se)
sh_per_se        3038 drivers/gpu/drm/radeon/si.c 	mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
sh_per_se        3044 drivers/gpu/drm/radeon/si.c 			u32 se_num, u32 sh_per_se,
sh_per_se        3053 drivers/gpu/drm/radeon/si.c 		for (j = 0; j < sh_per_se; j++) {
sh_per_se        3055 drivers/gpu/drm/radeon/si.c 			data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
sh_per_se        3056 drivers/gpu/drm/radeon/si.c 			disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
sh_per_se        3073 drivers/gpu/drm/radeon/si.c 		for (j = 0; j < sh_per_se; j++) {
sh_per_se        3076 drivers/gpu/drm/radeon/si.c 				data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
sh_per_se        3079 drivers/gpu/drm/radeon/si.c 				data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
sh_per_se        3083 drivers/gpu/drm/radeon/si.c 				data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);