set_rate_and_parent 272 drivers/clk/clk-composite.c clk_composite_ops->set_rate_and_parent = set_rate_and_parent 2046 drivers/clk/clk.c if (core->ops->set_rate_and_parent) { set_rate_and_parent 2048 drivers/clk/clk.c core->ops->set_rate_and_parent(core->hw, core->new_rate, set_rate_and_parent 3338 drivers/clk/clk.c if (core->ops->set_rate_and_parent && set_rate_and_parent 551 drivers/clk/microchip/clk-core.c .set_rate_and_parent = roclk_set_rate_and_parent, set_rate_and_parent 432 drivers/clk/mmp/clk-mix.c .set_rate_and_parent = mmp_clk_mix_set_rate_and_parent, set_rate_and_parent 838 drivers/clk/qcom/clk-rcg.c .set_rate_and_parent = clk_rcg_bypass2_set_rate_and_parent, set_rate_and_parent 850 drivers/clk/qcom/clk-rcg.c .set_rate_and_parent = clk_rcg_pixel_set_rate_and_parent, set_rate_and_parent 862 drivers/clk/qcom/clk-rcg.c .set_rate_and_parent = clk_rcg_esc_set_rate_and_parent, set_rate_and_parent 886 drivers/clk/qcom/clk-rcg.c .set_rate_and_parent = clk_dyn_rcg_set_rate_and_parent, set_rate_and_parent 366 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_rcg2_set_rate_and_parent, set_rate_and_parent 377 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent, set_rate_and_parent 503 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent, set_rate_and_parent 561 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_byte_set_rate_and_parent, set_rate_and_parent 631 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_byte2_set_rate_and_parent, set_rate_and_parent 721 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_pixel_set_rate_and_parent, set_rate_and_parent 808 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_gfx3d_set_rate_and_parent, set_rate_and_parent 947 drivers/clk/qcom/clk-rcg2.c .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent, set_rate_and_parent 227 drivers/clk/qcom/clk-regmap-mux-div.c .set_rate_and_parent = mux_div_set_rate_and_parent, set_rate_and_parent 39 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, set_rate_and_parent 64 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, set_rate_and_parent 77 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, set_rate_and_parent 118 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, set_rate_and_parent 130 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, set_rate_and_parent 142 drivers/clk/ti/dpll.c .set_rate_and_parent = &omap3_dpll4_set_rate_and_parent, set_rate_and_parent 235 include/linux/clk-provider.h int (*set_rate_and_parent)(struct clk_hw *hw,