set_pme_wa_enable  915 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable;
set_pme_wa_enable  939 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_pme_wa_enable = NULL;
set_pme_wa_enable  234 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		if (pp_smu->set_pme_wa_enable)
set_pme_wa_enable  235 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
set_pme_wa_enable  393 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		if (pp_smu->set_pme_wa_enable)
set_pme_wa_enable  394 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
set_pme_wa_enable 1425 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 			&& pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL)
set_pme_wa_enable  143 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	void (*set_pme_wa_enable)(struct pp_smu *pp);
set_pme_wa_enable  204 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_pme_wa_enable)(struct pp_smu *pp);