set_min_deep_sleep_dcfclk  918 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->rv_funcs.set_min_deep_sleep_dcfclk =
set_min_deep_sleep_dcfclk  932 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_min_deep_sleep_dcfclk =
set_min_deep_sleep_dcfclk  198 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 				pp_smu->set_min_deep_sleep_dcfclk) {
set_min_deep_sleep_dcfclk  201 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
set_min_deep_sleep_dcfclk  218 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 				pp_smu->set_min_deep_sleep_dcfclk) {
set_min_deep_sleep_dcfclk  221 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
set_min_deep_sleep_dcfclk  242 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk)
set_min_deep_sleep_dcfclk  243 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_deep_sleep_khz / 1000);
set_min_deep_sleep_dcfclk  130 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
set_min_deep_sleep_dcfclk  191 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int Mhz);