set_hard_min_uclk_by_freq  941 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		funcs->nv_funcs.set_hard_min_uclk_by_freq = pp_nv_set_hard_min_uclk_by_freq;
set_hard_min_uclk_by_freq  263 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		if (pp_smu && pp_smu->set_hard_min_uclk_by_freq)
set_hard_min_uclk_by_freq  264 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			pp_smu->set_hard_min_uclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dramclk_khz / 1000);
set_hard_min_uclk_by_freq  196 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	enum pp_smu_status (*set_hard_min_uclk_by_freq)(struct pp_smu *pp, int Mhz);