set_hard_min_socclk_by_freq 248 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) set_hard_min_socclk_by_freq 249 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_hard_min_socclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.socclk_khz / 1000); set_hard_min_socclk_by_freq 140 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz); set_hard_min_socclk_by_freq 201 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int Mhz);