set_hard_min_dcfclk_by_freq 920 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c funcs->rv_funcs.set_hard_min_dcfclk_by_freq = set_hard_min_dcfclk_by_freq 930 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c funcs->nv_funcs.set_hard_min_dcfclk_by_freq = set_hard_min_dcfclk_by_freq 197 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq && set_hard_min_dcfclk_by_freq 200 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000); set_hard_min_dcfclk_by_freq 217 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq && set_hard_min_dcfclk_by_freq 220 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000); set_hard_min_dcfclk_by_freq 235 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) set_hard_min_dcfclk_by_freq 236 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, clk_mgr_base->clks.dcfclk_khz / 1000); set_hard_min_dcfclk_by_freq 124 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz); set_hard_min_dcfclk_by_freq 185 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h enum pp_smu_status (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int Mhz);