serr_int 212 drivers/gpu/drm/i915/display/intel_fifo_underrun.c u32 serr_int = I915_READ(SERR_INT); serr_int 216 drivers/gpu/drm/i915/display/intel_fifo_underrun.c if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) serr_int 2210 drivers/gpu/drm/i915/i915_irq.c u32 serr_int = I915_READ(SERR_INT); serr_int 2213 drivers/gpu/drm/i915/i915_irq.c if (serr_int & SERR_INT_POISON) serr_int 2217 drivers/gpu/drm/i915/i915_irq.c if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) serr_int 2220 drivers/gpu/drm/i915/i915_irq.c I915_WRITE(SERR_INT, serr_int); serr_int 563 drivers/pci/hotplug/shpchp_hpc.c u32 slot_reg, serr_int; serr_int 583 drivers/pci/hotplug/shpchp_hpc.c serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); serr_int 584 drivers/pci/hotplug/shpchp_hpc.c serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | serr_int 586 drivers/pci/hotplug/shpchp_hpc.c serr_int &= ~SERR_INTR_RSVDZ_MASK; serr_int 587 drivers/pci/hotplug/shpchp_hpc.c shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); serr_int 775 drivers/pci/hotplug/shpchp_hpc.c u32 serr_int, slot_reg, intr_loc, intr_loc2; serr_int 790 drivers/pci/hotplug/shpchp_hpc.c serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); serr_int 791 drivers/pci/hotplug/shpchp_hpc.c serr_int |= GLOBAL_INTR_MASK; serr_int 792 drivers/pci/hotplug/shpchp_hpc.c serr_int &= ~SERR_INTR_RSVDZ_MASK; serr_int 793 drivers/pci/hotplug/shpchp_hpc.c shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); serr_int 805 drivers/pci/hotplug/shpchp_hpc.c serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); serr_int 806 drivers/pci/hotplug/shpchp_hpc.c serr_int &= ~SERR_INTR_RSVDZ_MASK; serr_int 807 drivers/pci/hotplug/shpchp_hpc.c shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); serr_int 843 drivers/pci/hotplug/shpchp_hpc.c serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); serr_int 844 drivers/pci/hotplug/shpchp_hpc.c serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK); serr_int 845 drivers/pci/hotplug/shpchp_hpc.c shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);