CM0_CM_3DLUT_READ_WRITE_CONTROL 356 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_WRITE_EN_MASK, mask_sh), \ CM0_CM_3DLUT_READ_WRITE_CONTROL 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_RAM_SEL, mask_sh), \ CM0_CM_3DLUT_READ_WRITE_CONTROL 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_30BIT_EN, mask_sh), \ CM0_CM_3DLUT_READ_WRITE_CONTROL 359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_CONFIG_STATUS, mask_sh), \ CM0_CM_3DLUT_READ_WRITE_CONTROL 360 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CM0_CM_3DLUT_READ_WRITE_CONTROL, CM_3DLUT_READ_SEL, mask_sh), \