send_regs          28 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	GEM_BUG_ON(!guc->send_regs.base);
send_regs          29 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	GEM_BUG_ON(!guc->send_regs.count);
send_regs          30 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	GEM_BUG_ON(i >= guc->send_regs.count);
send_regs          32 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	return _MMIO(guc->send_regs.base + 4 * i);
send_regs          42 drivers/gpu/drm/i915/gt/uc/intel_guc.c 		guc->send_regs.base =
send_regs          44 drivers/gpu/drm/i915/gt/uc/intel_guc.c 		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
send_regs          46 drivers/gpu/drm/i915/gt/uc/intel_guc.c 		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
send_regs          47 drivers/gpu/drm/i915/gt/uc/intel_guc.c 		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
send_regs          51 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	for (i = 0; i < guc->send_regs.count; i++) {
send_regs          56 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	guc->send_regs.fw_domains = fw_domains;
send_regs         354 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	GEM_BUG_ON(len > guc->send_regs.count);
send_regs         364 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
send_regs         394 drivers/gpu/drm/i915/gt/uc/intel_guc.c 		int count = min(response_buf_size, guc->send_regs.count - 1);
send_regs         405 drivers/gpu/drm/i915/gt/uc/intel_guc.c 	intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
send_regs          67 drivers/gpu/drm/i915/gt/uc/intel_guc.h 	} send_regs;