sel_reg          1085 drivers/base/regmap/regmap.c 			unsigned sel_reg = config->ranges[j].selector_reg;
sel_reg          1094 drivers/base/regmap/regmap.c 			if (range_cfg->range_min <= sel_reg &&
sel_reg          1095 drivers/base/regmap/regmap.c 			    sel_reg <= range_cfg->range_max) {
sel_reg           507 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 	if (cluster->sel_reg)
sel_reg           508 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c 		in += CRASHDUMP_WRITE(in, cluster->sel_reg, cluster->sel_val);
sel_reg            54 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h 		.sel_reg = _sel_reg, .sel_val = _sel_val }
sel_reg            61 drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h 	u32 sel_reg;
sel_reg           160 drivers/mtd/nand/raw/s3c2410.c 	void __iomem			*sel_reg;
sel_reg           417 drivers/mtd/nand/raw/s3c2410.c 	cur = readl(info->sel_reg);
sel_reg           435 drivers/mtd/nand/raw/s3c2410.c 	writel(cur, info->sel_reg);
sel_reg           872 drivers/mtd/nand/raw/s3c2410.c 		info->sel_reg   = regs + S3C2410_NFCONF;
sel_reg           880 drivers/mtd/nand/raw/s3c2410.c 		info->sel_reg   = regs + S3C2440_NFCONT;
sel_reg           890 drivers/mtd/nand/raw/s3c2410.c 		info->sel_reg   = regs + S3C2440_NFCONT;
sel_reg          1214 drivers/mtd/nand/raw/s3c2410.c 		info->save_sel = readl(info->sel_reg);
sel_reg          1221 drivers/mtd/nand/raw/s3c2410.c 		writel(info->save_sel | info->sel_bit, info->sel_reg);
sel_reg          1240 drivers/mtd/nand/raw/s3c2410.c 		sel = readl(info->sel_reg);
sel_reg          1243 drivers/mtd/nand/raw/s3c2410.c 		writel(sel, info->sel_reg);