sel_clk            16 drivers/gpu/drm/armada/armada_510.c 	struct clk *sel_clk;
sel_clk           124 drivers/gpu/drm/armada/armada_510.c 		v->sel_clk = res.clk;
sel_clk           146 drivers/gpu/drm/armada/armada_510.c 	if (!dcrtc->clk && v->sel_clk) {
sel_clk           147 drivers/gpu/drm/armada/armada_510.c 		if (!WARN_ON(clk_prepare_enable(v->sel_clk)))
sel_clk           148 drivers/gpu/drm/armada/armada_510.c 			dcrtc->clk = v->sel_clk;
sel_clk          1432 drivers/gpu/drm/i2c/tda998x_drv.c 	u8 reg, div, rep, sel_clk;
sel_clk          1510 drivers/gpu/drm/i2c/tda998x_drv.c 	sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
sel_clk          1555 drivers/gpu/drm/i2c/tda998x_drv.c 	reg_write(priv, REG_SEL_CLK, sel_clk);
sel_clk           653 drivers/gpu/drm/nouveau/dispnv04/crtc.c 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
sel_clk           674 drivers/gpu/drm/nouveau/dispnv04/crtc.c 	state->sel_clk = saved->sel_clk & ~(0x5 << 16);
sel_clk           217 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		state->sel_clk |= bits1618;
sel_clk           219 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		state->sel_clk &= ~bits1618;
sel_clk           236 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
sel_clk           237 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
sel_clk           239 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		state->sel_clk &= ~0xf0;
sel_clk           240 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		state->sel_clk |= (head ? 0x40 : 0x10) << shift;
sel_clk           554 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
sel_clk           555 drivers/gpu/drm/nouveau/dispnv04/dfp.c 		nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
sel_clk           557 drivers/gpu/drm/nouveau/dispnv04/dfp.c 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
sel_clk            76 drivers/gpu/drm/nouveau/dispnv04/disp.h 	uint32_t sel_clk;
sel_clk           404 drivers/gpu/drm/nouveau/dispnv04/hw.c 		state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
sel_clk           481 drivers/gpu/drm/nouveau/dispnv04/hw.c 		NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
sel_clk           219 drivers/gpu/drm/nouveau/nouveau_bios.c 	uint32_t sel_clk_binding, sel_clk;
sel_clk           248 drivers/gpu/drm/nouveau/nouveau_bios.c 	sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
sel_clk           249 drivers/gpu/drm/nouveau/nouveau_bios.c 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
sel_clk           640 drivers/gpu/drm/nouveau/nouveau_bios.c 	uint32_t sel_clk_binding, sel_clk;
sel_clk           672 drivers/gpu/drm/nouveau/nouveau_bios.c 	sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
sel_clk           673 drivers/gpu/drm/nouveau/nouveau_bios.c 	NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
sel_clk           390 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c 			u32 sel_clk = nvkm_rd32(device, 0x680524);
sel_clk           391 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c 			if ((info->reg == 0x680508 && sel_clk & 0x20) ||
sel_clk           392 drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c 			    (info->reg == 0x680520 && sel_clk & 0x80)) {
sel_clk            99 drivers/spi/spi-mt65xx.c 	struct clk *parent_clk, *sel_clk, *spi_clk;
sel_clk           722 drivers/spi/spi-mt65xx.c 	mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk");
sel_clk           723 drivers/spi/spi-mt65xx.c 	if (IS_ERR(mdata->sel_clk)) {
sel_clk           724 drivers/spi/spi-mt65xx.c 		ret = PTR_ERR(mdata->sel_clk);
sel_clk           742 drivers/spi/spi-mt65xx.c 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);