se_mask          1381 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	unsigned se_mask[4];
se_mask          1384 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
se_mask          1385 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
se_mask          1386 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
se_mask          1387 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
se_mask          1399 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
se_mask          1402 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 			if (!se_mask[idx])
se_mask          1678 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	unsigned se_mask[4];
se_mask          1681 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
se_mask          1682 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
se_mask          1683 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
se_mask          1684 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
se_mask          1690 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
se_mask          1691 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			     (!se_mask[2] && !se_mask[3]))) {
se_mask          1694 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		if (!se_mask[0] && !se_mask[1]) {
se_mask          1709 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
se_mask          1712 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			if (!se_mask[idx]) {
se_mask          3542 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	unsigned se_mask[4];
se_mask          3545 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
se_mask          3546 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
se_mask          3547 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
se_mask          3548 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
se_mask          3554 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
se_mask          3555 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			     (!se_mask[2] && !se_mask[3]))) {
se_mask          3558 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		if (!se_mask[0] && !se_mask[1]) {
se_mask          3573 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
se_mask          3576 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			if (!se_mask[idx]) {
se_mask            98 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c 		uint32_t *se_mask)
se_mask           123 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c 			se_mask[se] |= 1 << cu;
se_mask           120 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h 		uint32_t *se_mask);
se_mask            48 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
se_mask            54 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 		q->cu_mask, q->cu_mask_count, se_mask);
se_mask            57 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	m->compute_static_thread_mgmt_se0 = se_mask[0];
se_mask            58 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	m->compute_static_thread_mgmt_se1 = se_mask[1];
se_mask            59 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	m->compute_static_thread_mgmt_se2 = se_mask[2];
se_mask            60 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	m->compute_static_thread_mgmt_se3 = se_mask[3];
se_mask            48 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
se_mask            54 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 		q->cu_mask, q->cu_mask_count, se_mask);
se_mask            57 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	m->compute_static_thread_mgmt_se0 = se_mask[0];
se_mask            58 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	m->compute_static_thread_mgmt_se1 = se_mask[1];
se_mask            59 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	m->compute_static_thread_mgmt_se2 = se_mask[2];
se_mask            60 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	m->compute_static_thread_mgmt_se3 = se_mask[3];
se_mask            49 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	uint32_t se_mask[KFD_MAX_NUM_SE] = {0};
se_mask            55 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 		q->cu_mask, q->cu_mask_count, se_mask);
se_mask            58 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se0 = se_mask[0];
se_mask            59 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se1 = se_mask[1];
se_mask            60 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se2 = se_mask[2];
se_mask            61 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se3 = se_mask[3];
se_mask            62 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se4 = se_mask[4];
se_mask            63 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se5 = se_mask[5];
se_mask            64 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se6 = se_mask[6];
se_mask            65 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->compute_static_thread_mgmt_se7 = se_mask[7];
se_mask            51 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
se_mask            57 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 		q->cu_mask, q->cu_mask_count, se_mask);
se_mask            60 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	m->compute_static_thread_mgmt_se0 = se_mask[0];
se_mask            61 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	m->compute_static_thread_mgmt_se1 = se_mask[1];
se_mask            62 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	m->compute_static_thread_mgmt_se2 = se_mask[2];
se_mask            63 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	m->compute_static_thread_mgmt_se3 = se_mask[3];
se_mask            42 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	enc110->se_shift->field_name, enc110->se_mask->field_name
se_mask           329 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
se_mask           333 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		if (enc110->se_mask->DP_VID_N_MUL)
se_mask           451 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 		if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
se_mask           574 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
se_mask           623 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
se_mask           746 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
se_mask           747 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			enc110->se_mask->HDMI_AVI_INFO_SEND) {
se_mask           781 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
se_mask           782 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 			enc110->se_mask->HDMI_AVI_INFO_SEND) {
se_mask           790 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (enc110->se_mask->HDMI_DB_DISABLE) {
se_mask           900 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
se_mask          1045 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN)
se_mask          1661 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	const struct dce_stream_encoder_mask *se_mask)
se_mask          1669 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c 	enc110->se_mask = se_mask;
se_mask           701 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	const struct dce_stream_encoder_mask *se_mask;
se_mask           711 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h 	const struct dce_stream_encoder_mask *se_mask);
se_mask           248 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c static const struct dce_stream_encoder_mask se_mask = {
se_mask           446 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 					&stream_enc_regs[eng_id], &se_shift, &se_mask);
se_mask           274 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c static const struct dce_stream_encoder_mask se_mask = {
se_mask           488 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 					&se_shift, &se_mask);
se_mask           281 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c static const struct dce_stream_encoder_mask se_mask = {
se_mask           466 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 					&se_shift, &se_mask);
se_mask           292 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c static const struct dce_stream_encoder_mask se_mask = {
se_mask           699 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 					&se_shift, &se_mask);
se_mask           265 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c static const struct dce_stream_encoder_mask se_mask = {
se_mask           558 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 					&se_shift, &se_mask);
se_mask           248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c static const struct dcn10_stream_encoder_mask se_mask = {
se_mask           821 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 					&se_shift, &se_mask);
se_mask            42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	enc1->se_shift->field_name, enc1->se_mask->field_name
se_mask          1601 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	const struct dcn10_stream_encoder_mask *se_mask)
se_mask          1609 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 	enc1->se_mask = se_mask;
se_mask           508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	const struct dcn10_stream_encoder_mask *se_mask;
se_mask           518 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h 	const struct dcn10_stream_encoder_mask *se_mask);
se_mask           562 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c static const struct dcn10_stream_encoder_mask se_mask = {
se_mask          1228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 					&se_shift, &se_mask);
se_mask            42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	enc1->se_shift->field_name, enc1->se_mask->field_name
se_mask           605 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	const struct dcn10_stream_encoder_mask *se_mask)
se_mask           613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c 	enc1->se_mask = se_mask;
se_mask            95 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h 	const struct dcn10_stream_encoder_mask *se_mask);
se_mask           636 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c static const struct dcn10_stream_encoder_mask se_mask = {
se_mask          1378 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 					&se_shift, &se_mask);
se_mask           637 drivers/ntb/hw/idt/ntb_hw_idt.c 	u32 part_mask, port_mask, se_mask;
se_mask           669 drivers/ntb/hw/idt/ntb_hw_idt.c 	se_mask = ~(IDT_SEMSK_LINKUP | IDT_SEMSK_LINKDN | IDT_SEMSK_GSIGNAL);
se_mask           670 drivers/ntb/hw/idt/ntb_hw_idt.c 	idt_sw_write(ndev, IDT_SW_SEMSK, se_mask);