se_base           126 drivers/gpu/drm/arm/malidp_drv.c 	u32 se_control = hwdev->hw->map.se_base +
se_base           931 drivers/gpu/drm/arm/malidp_hw.c 			.se_base = MALIDP500_SE_BASE,
se_base           980 drivers/gpu/drm/arm/malidp_hw.c 			.se_base = MALIDP550_SE_BASE,
se_base          1029 drivers/gpu/drm/arm/malidp_hw.c 			.se_base = MALIDP550_SE_BASE,
se_base          1294 drivers/gpu/drm/arm/malidp_hw.c 	status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
se_base          1303 drivers/gpu/drm/arm/malidp_hw.c 	mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ);
se_base           105 drivers/gpu/drm/arm/malidp_hw.h 	const u16 se_base;
se_base           292 drivers/gpu/drm/arm/malidp_hw.h 		return hwdev->hw->map.se_base;
se_base           370 drivers/gpu/drm/arm/malidp_hw.h 	u32 image_enh = hwdev->hw->map.se_base +