sdr_base           33 arch/arm/mach-socfpga/core.h u32 socfpga_sdram_self_refresh(u32 sdr_base);
sdr_base           23 arch/arm/mach-socfpga/pm.c static u32 (*socfpga_sdram_self_refresh_in_ocram)(u32 sdr_base);
sdr_base          643 arch/powerpc/platforms/4xx/pci.c 	unsigned int		sdr_base;
sdr_base          673 arch/powerpc/platforms/4xx/pci.c 		val = mfdcri(SDR0, port->sdr_base + sdr_offset);
sdr_base          857 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
sdr_base          858 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
sdr_base          860 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
sdr_base          861 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
sdr_base          862 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
sdr_base          863 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
sdr_base          864 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
sdr_base          866 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
sdr_base          868 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
sdr_base          870 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
sdr_base          872 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
sdr_base          875 arch/powerpc/platforms/4xx/pci.c 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
sdr_base          965 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
sdr_base          966 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
sdr_base          967 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
sdr_base          996 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
sdr_base          997 arch/powerpc/platforms/4xx/pci.c 	       mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
sdr_base         1013 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
sdr_base         1014 arch/powerpc/platforms/4xx/pci.c 	       (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
sdr_base         1080 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
sdr_base         1081 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
sdr_base         1082 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
sdr_base         1092 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
sdr_base         1093 arch/powerpc/platforms/4xx/pci.c 		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
sdr_base         1097 arch/powerpc/platforms/4xx/pci.c 	val = PESDR0_460EX_RSTSTA - port->sdr_base;
sdr_base         1102 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
sdr_base         1103 arch/powerpc/platforms/4xx/pci.c 			(mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
sdr_base         1210 arch/powerpc/platforms/4xx/pci.c 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
sdr_base         1213 arch/powerpc/platforms/4xx/pci.c 		dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
sdr_base         1216 arch/powerpc/platforms/4xx/pci.c 	dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
sdr_base         1281 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
sdr_base         1286 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
sdr_base         1288 arch/powerpc/platforms/4xx/pci.c 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
sdr_base         1292 arch/powerpc/platforms/4xx/pci.c 	while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
sdr_base         1296 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
sdr_base         1308 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
sdr_base         1311 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
sdr_base         1312 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
sdr_base         1313 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
sdr_base         1314 arch/powerpc/platforms/4xx/pci.c 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
sdr_base         1323 arch/powerpc/platforms/4xx/pci.c 	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
sdr_base         1524 arch/powerpc/platforms/4xx/pci.c 	if (port->sdr_base) {
sdr_base         1542 arch/powerpc/platforms/4xx/pci.c 		dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
sdr_base         2121 arch/powerpc/platforms/4xx/pci.c 		port->sdr_base = *pval;