sdmax_rlcx_rb_cntl  148 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
sdmax_rlcx_rb_cntl  196 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
sdmax_rlcx_rb_cntl  506 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
sdmax_rlcx_rb_cntl  554 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
sdmax_rlcx_rb_cntl  407 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
sdmax_rlcx_rb_cntl  451 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
sdmax_rlcx_rb_cntl  405 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
sdmax_rlcx_rb_cntl  453 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
sdmax_rlcx_rb_cntl  355 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c 	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
sdmax_rlcx_rb_cntl  373 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c 	m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
sdmax_rlcx_rb_cntl  354 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c 	m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
sdmax_rlcx_rb_cntl  544 drivers/gpu/drm/amd/include/v10_structs.h 	uint32_t sdmax_rlcx_rb_cntl;
sdmax_rlcx_rb_cntl   28 drivers/gpu/drm/amd/include/v9_structs.h 	uint32_t sdmax_rlcx_rb_cntl;
sdmax_rlcx_rb_cntl   28 drivers/gpu/drm/amd/include/vi_structs.h 	uint32_t sdmax_rlcx_rb_cntl;