sdma_rlc_rb_cntl  239 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	uint32_t sdma_rlc_rb_cntl;
sdma_rlc_rb_cntl  245 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sdma_rlc_rb_cntl  247 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
sdma_rlc_rb_cntl  622 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	uint32_t sdma_rlc_rb_cntl;
sdma_rlc_rb_cntl  628 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sdma_rlc_rb_cntl  630 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
sdma_rlc_rb_cntl  423 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 		m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
sdma_rlc_rb_cntl  467 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
sdma_rlc_rb_cntl  528 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	uint32_t sdma_rlc_rb_cntl;
sdma_rlc_rb_cntl  533 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sdma_rlc_rb_cntl  535 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
sdma_rlc_rb_cntl  521 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	uint32_t sdma_rlc_rb_cntl;
sdma_rlc_rb_cntl  526 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sdma_rlc_rb_cntl  528 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
sdma_rlc_rb_cntl  518 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	uint32_t sdma_rlc_rb_cntl;
sdma_rlc_rb_cntl  524 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sdma_rlc_rb_cntl  526 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 	if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
sdma_rlc_rb_cntl  241 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c 	m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
sdma_rlc_rb_cntl  159 drivers/gpu/drm/amd/include/cik_structs.h 	uint32_t sdma_rlc_rb_cntl;