sdma_offsets 47 drivers/gpu/drm/amd/amdgpu/cik_sdma.c static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = sdma_offsets 183 drivers/gpu/drm/amd/amdgpu/cik_sdma.c return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; sdma_offsets 197 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], sdma_offsets 318 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); sdma_offsets 320 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 321 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); sdma_offsets 377 drivers/gpu/drm/amd/amdgpu/cik_sdma.c f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); sdma_offsets 382 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], sdma_offsets 384 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], sdma_offsets 392 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); sdma_offsets 415 drivers/gpu/drm/amd/amdgpu/cik_sdma.c me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); sdma_offsets 420 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); sdma_offsets 448 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); sdma_offsets 449 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); sdma_offsets 455 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], sdma_offsets 458 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); sdma_offsets 459 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); sdma_offsets 468 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 471 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); sdma_offsets 472 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); sdma_offsets 473 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); sdma_offsets 474 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); sdma_offsets 477 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], sdma_offsets 479 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], sdma_offsets 484 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); sdma_offsets 485 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); sdma_offsets 488 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); sdma_offsets 491 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], sdma_offsets 499 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); sdma_offsets 563 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); sdma_offsets 565 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); sdma_offsets 566 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); sdma_offsets 60 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = sdma_offsets 210 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; sdma_offsets 226 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); sdma_offsets 351 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); sdma_offsets 353 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 354 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); sdma_offsets 356 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); sdma_offsets 393 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); sdma_offsets 398 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); sdma_offsets 426 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); sdma_offsets 427 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); sdma_offsets 432 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], sdma_offsets 435 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); sdma_offsets 439 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); sdma_offsets 446 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 449 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); sdma_offsets 450 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); sdma_offsets 451 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); sdma_offsets 452 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); sdma_offsets 455 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], sdma_offsets 457 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], sdma_offsets 462 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); sdma_offsets 463 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); sdma_offsets 466 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); sdma_offsets 470 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 472 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); sdma_offsets 478 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); sdma_offsets 74 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = sdma_offsets 372 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; sdma_offsets 399 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); sdma_offsets 525 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); sdma_offsets 527 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 528 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); sdma_offsets 530 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); sdma_offsets 586 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); sdma_offsets 593 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], sdma_offsets 595 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], sdma_offsets 605 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); sdma_offsets 628 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); sdma_offsets 633 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); sdma_offsets 664 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); sdma_offsets 665 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); sdma_offsets 670 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], sdma_offsets 673 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); sdma_offsets 677 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); sdma_offsets 684 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 688 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); sdma_offsets 690 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); sdma_offsets 691 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); sdma_offsets 694 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], sdma_offsets 696 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], sdma_offsets 701 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); sdma_offsets 702 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); sdma_offsets 704 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]); sdma_offsets 713 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell); sdma_offsets 718 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], sdma_offsets 720 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], sdma_offsets 722 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); sdma_offsets 725 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); sdma_offsets 734 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl); sdma_offsets 738 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 740 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); sdma_offsets 746 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); sdma_offsets 1448 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); sdma_offsets 1458 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); sdma_offsets 1462 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); sdma_offsets 1473 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); sdma_offsets 1487 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); sdma_offsets 1491 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); sdma_offsets 1495 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); sdma_offsets 1499 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); sdma_offsets 1542 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]); sdma_offsets 1547 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); sdma_offsets 30 drivers/gpu/drm/amd/amdgpu/si_dma.c const u32 sdma_offsets[SDMA_MAX_INSTANCE] = sdma_offsets 51 drivers/gpu/drm/amd/amdgpu/si_dma.c return (RREG32(DMA_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; sdma_offsets 59 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[me], sdma_offsets 121 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); sdma_offsets 123 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 141 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); sdma_offsets 142 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); sdma_offsets 150 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); sdma_offsets 153 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); sdma_offsets 154 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); sdma_offsets 158 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); sdma_offsets 159 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); sdma_offsets 163 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); sdma_offsets 170 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); sdma_offsets 172 drivers/gpu/drm/amd/amdgpu/si_dma.c dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); sdma_offsets 174 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); sdma_offsets 177 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); sdma_offsets 178 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE);