sdm_din           110 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	u32 sdm_din;
sdm_din           168 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	pll->sdm_din = (val >> GPCPLL_CFG2_SDM_DIN_SHIFT) &
sdm_din           178 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 		  pll->sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT);
sdm_din           225 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c gm20b_dvfs_calc_ndiv(struct gm20b_clk *clk, u32 n_eff, u32 *n_int, u32 *sdm_din)
sdm_din           259 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	*sdm_din = (rem >> BITS_PER_BYTE) & MASK(GPCPLL_CFG2_SDM_DIN_WIDTH);
sdm_din           262 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 		   n_eff, *n_int, *sdm_din);
sdm_din           271 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	u32 n_int, sdm_din;
sdm_din           275 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	gm20b_dvfs_calc_ndiv(clk, n, &n_int, &sdm_din);
sdm_din           280 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	if (n_int == pll.base.n && sdm_din == pll.sdm_din)
sdm_din           291 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 		  sdm_din << GPCPLL_CFG2_SDM_DIN_NEW_SHIFT);
sdm_din           310 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 		  sdm_din << GPCPLL_CFG2_SDM_DIN_SHIFT);
sdm_din           365 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	u32 n_int, sdm_din;
sdm_din           370 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	gm20b_dvfs_calc_ndiv(clk, pll->n, &n_int, &sdm_din);
sdm_din           372 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 	pdiv_only = cur_pll.base.n == n_int && cur_pll.sdm_din == sdm_din &&
sdm_din           412 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c 		cur_pll.sdm_din = sdm_din;