sdm_cfg1          136 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
sdm_cfg1          184 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	sdm_cfg1 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1);
sdm_cfg1          185 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	sdm_cfg1 &= ~DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
sdm_cfg1          189 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(
sdm_cfg1          197 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		sdm_cfg1 |= DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(0);
sdm_cfg1          203 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	DBG("sdm_cfg1=%d", sdm_cfg1);
sdm_cfg1          216 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1, sdm_cfg1);