sdm_cfg0 136 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3; sdm_cfg0 187 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm_cfg0 = 0x0; sdm_cfg0 188 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); sdm_cfg0 194 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm_cfg0 = DSI_28nm_PHY_PLL_SDM_CFG0_BYP; sdm_cfg0 195 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV( sdm_cfg0 202 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c DBG("sdm_cfg0=%d", sdm_cfg0); sdm_cfg0 230 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0, sdm_cfg0);