sdh0_lock 176 drivers/clk/mmp/clk-of-pxa168.c static DEFINE_SPINLOCK(sdh0_lock); sdh0_lock 190 drivers/clk/mmp/clk-of-pxa168.c {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, sdh0_lock 206 drivers/clk/mmp/clk-of-pxa168.c {PXA168_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, sdh0_lock 142 drivers/clk/mmp/clk-of-pxa1928.c static DEFINE_SPINLOCK(sdh0_lock); sdh0_lock 152 drivers/clk/mmp/clk-of-pxa1928.c {0, "sdh_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 8, 2, 0, &sdh0_lock}, sdh0_lock 156 drivers/clk/mmp/clk-of-pxa1928.c {0, "sdh_div", "sdh_mux", 0, PXA1928_CLK_SDH0 * 4, 10, 4, CLK_DIVIDER_ONE_BASED, &sdh0_lock}, sdh0_lock 163 drivers/clk/mmp/clk-of-pxa1928.c {PXA1928_CLK_SDH0, "sdh0_clk", "sdh_div", CLK_SET_RATE_PARENT, PXA1928_CLK_SDH0 * 4, 0x1b, 0x1b, 0x0, 0, &sdh0_lock}, sdh0_lock 182 drivers/clk/mmp/clk-of-pxa910.c static DEFINE_SPINLOCK(sdh0_lock); sdh0_lock 196 drivers/clk/mmp/clk-of-pxa910.c {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, sdh0_lock 212 drivers/clk/mmp/clk-of-pxa910.c {PXA910_CLK_SDH0, "sdh0_clk", "sdh0_mux", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh0_lock},