sclk_table 417 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c phm_ppt_v1_clock_voltage_dependency_table *sclk_table; sclk_table 431 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sclk_table = kzalloc(table_size, GFP_KERNEL); sclk_table 433 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c if (NULL == sclk_table) sclk_table 436 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sclk_table->count = (uint32_t)tonga_table->ucNumEntries; sclk_table 444 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c entries, sclk_table, i); sclk_table 463 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sclk_table = kzalloc(table_size, GFP_KERNEL); sclk_table 465 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c if (NULL == sclk_table) sclk_table 468 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c sclk_table->count = (uint32_t)polaris_table->ucNumEntries; sclk_table 476 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c entries, sclk_table, i); sclk_table 486 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c *pp_tonga_sclk_dep_table = sclk_table; sclk_table 633 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &data->dpm_table.sclk_table, sclk_table 691 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.count = 0; sclk_table 694 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != sclk_table 696 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = sclk_table 698 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; sclk_table 699 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.count++; sclk_table 785 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.count = 0; sclk_table 787 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != sclk_table 790 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = sclk_table 793 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = sclk_table 795 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.count++; sclk_table 838 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->golden_dpm_table.sclk_table.count; sclk_table 840 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) { sclk_table 841 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; sclk_table 906 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < data->dpm_table.sclk_table.count; i++) { sclk_table 908 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->dpm_table.sclk_table.dpm_levels[i].value) { sclk_table 1703 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; sclk_table 1715 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table = table_info->vdd_dep_on_sclk; sclk_table 1717 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (j = 1; j < sclk_table->count; j++) { sclk_table 1718 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk_table->entries[j].clk == sclk && sclk_table 1719 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[j].cks_enable == 0) { sclk_table 1749 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table = table_info->vdd_dep_on_sclk; sclk_table 1751 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (j = 1; j < sclk_table->count; j++) { sclk_table 1752 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk_table->entries[j].clk == sclk && sclk_table 1753 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[j].cks_enable == 0) { sclk_table 1851 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1859 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { sclk_table 1860 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c voltage_id = sclk_table->entries[entry_id].vddInd; sclk_table 1861 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[entry_id].vddgfx = sclk_table 1865 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { sclk_table 1866 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c voltage_id = sclk_table->entries[entry_id].vddInd; sclk_table 1867 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[entry_id].vddc = sclk_table 1932 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; sclk_table 1936 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { sclk_table 1937 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) sclk_table 1938 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + sclk_table 1939 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[entry_id].vdd_offset - 0xFFFF; sclk_table 1941 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + sclk_table 1942 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[entry_id].vdd_offset; sclk_table 1944 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->entries[entry_id].vddc = sclk_table 2740 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / sclk_table 3599 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); sclk_table 3608 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 3609 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk == sclk_table->dpm_levels[i].value) sclk_table 3613 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (i >= sclk_table->count) { sclk_table 3614 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk > sclk_table->dpm_levels[i-1].value) { sclk_table 3616 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->dpm_levels[i-1].value = sclk; sclk_table 3660 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 3661 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) sclk_table 3769 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (count = 0; count < dpm_table->sclk_table.count; count++) { sclk_table 3770 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; sclk_table 3771 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; sclk_table 3836 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(data->dpm_table.sclk_table), sclk_table 3864 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); sclk_table 4445 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); sclk_table 4459 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 4460 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (clock > sclk_table->dpm_levels[i].value) sclk_table 4466 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < sclk_table->count; i++) sclk_table 4468 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c i, sclk_table->dpm_levels[i].value / 100, sclk_table 4525 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, sclk_table 4569 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); sclk_table 4571 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(data->golden_dpm_table.sclk_table); sclk_table 4572 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c int value = sclk_table->dpm_levels[sclk_table->count - 1].value; sclk_table 4586 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c &(data->golden_dpm_table.sclk_table); sclk_table 4656 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct phm_clock_voltage_dependency_table *sclk_table; sclk_table 4667 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; sclk_table 4668 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c for (i = 0; i < sclk_table->count; i++) sclk_table 4669 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->clock[i] = sclk_table->entries[i].clk * 10; sclk_table 4670 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->count = sclk_table->count; sclk_table 4777 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); sclk_table 4786 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c clocks->engine_max_clock = sclk_table->count > 1 ? sclk_table 4787 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->dpm_levels[sclk_table->count-1].value : sclk_table 4788 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->dpm_levels[0].value; sclk_table 4826 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk || sclk_table 4829 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, sclk_table 104 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h struct smu7_single_dpm_table sclk_table; sclk_table 1516 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c struct phm_clock_voltage_dependency_table *sclk_table = sclk_table 1528 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c for (i = 0; i < sclk_table->count; i++) sclk_table 1530 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c i, sclk_table->entries[i].clk / 100, sclk_table 3290 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); sclk_table 3298 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 3299 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (sclk == sclk_table->dpm_levels[i].value) sclk_table 3303 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (i >= sclk_table->count) { sclk_table 3304 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (sclk > sclk_table->dpm_levels[i-1].value) { sclk_table 3306 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c sclk_table->dpm_levels[i-1].value = sclk; sclk_table 4471 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); sclk_table 4488 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c for (i = 0; i < sclk_table->count; i++) sclk_table 4490 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c i, sclk_table->dpm_levels[i].value / 100, sclk_table 4751 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); sclk_table 4754 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c int value = sclk_table->dpm_levels[sclk_table->count - 1].value; sclk_table 2511 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); sclk_table 2514 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c int value = sclk_table->dpm_levels[sclk_table->count - 1].value; sclk_table 1442 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c struct vega20_single_dpm_table *sclk_table = sclk_table 1446 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c int value = sclk_table->dpm_levels[sclk_table->count - 1].value; sclk_table 484 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 486 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 492 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (i == (dpm_table->sclk_table.count - 1)) sclk_table 499 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; sclk_table 501 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 1658 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c for (i = 0; i < data->dpm_table.sclk_table.count; i++) { sclk_table 1661 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 1694 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c result = phm_find_boot_level(&(data->dpm_table.sclk_table), sclk_table 1026 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 1028 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 1042 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c levels[dpm_table->sclk_table.count - 1].DisplayWatermark = sclk_table 1046 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (uint8_t)dpm_table->sclk_table.count; sclk_table 1048 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 1055 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) sclk_table 1080 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 2; i < dpm_table->sclk_table.count; i++) sclk_table 1320 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_table.sclk_table.dpm_levels[0].value; sclk_table 1537 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < data->dpm_table.sclk_table.count; i++) { sclk_table 1540 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c data->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 1615 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c result = phm_find_boot_level(&(data->dpm_table.sclk_table), sclk_table 1676 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1706 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 1708 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk_table->entries[i].cks_enable << i; sclk_table 1710 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / sclk_table 1711 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); sclk_table 1713 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / sclk_table 1714 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); sclk_table 1717 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); sclk_table 980 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 982 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 996 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (dpm_table->sclk_table.count > 1) sclk_table 997 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = sclk_table 1001 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (uint8_t)dpm_table->sclk_table.count; sclk_table 1003 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 1026 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 2; i < dpm_table->sclk_table.count; i++) { sclk_table 1621 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c for (i = 0; i < data->dpm_table.sclk_table.count; i++) { sclk_table 1624 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 1657 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c result = phm_find_boot_level(&(data->dpm_table.sclk_table), sclk_table 1001 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 1004 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 1019 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (uint8_t)dpm_table->sclk_table.count; sclk_table 1021 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 1029 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) sclk_table 1054 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 2; i < dpm_table->sclk_table.count; i++) sclk_table 1370 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { sclk_table 1373 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c hw_data->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 1459 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c result = phm_find_boot_level(&(data->dpm_table.sclk_table), sclk_table 1519 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1556 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 1558 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_table->entries[i].cks_enable << i; sclk_table 1560 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \ sclk_table 1561 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); sclk_table 1562 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \ sclk_table 1563 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (2522480 - sclk_table->entries[i].clk/100 * 115764/100)); sclk_table 1565 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \ sclk_table 1566 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000))); sclk_table 1567 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \ sclk_table 1568 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000))); sclk_table 1573 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_table->entries[i].cks_voffset) * 100 + 624) / 625); sclk_table 1655 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1744 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625); sclk_table 1745 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100); sclk_table 710 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 712 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 726 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c if (dpm_table->sclk_table.count > 1) sclk_table 727 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = sclk_table 731 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (uint8_t)dpm_table->sclk_table.count; sclk_table 733 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 740 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 770 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 2; i < dpm_table->sclk_table.count; i++) sclk_table 1497 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < data->dpm_table.sclk_table.count; i++) { sclk_table 1500 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 1533 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c result = phm_find_boot_level(&(data->dpm_table.sclk_table), sclk_table 1584 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1620 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 1622 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk_table->entries[i].cks_enable << i; sclk_table 1625 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (sclk_table->entries[i].clk/100) / 10000) * 1000 / sclk_table 1626 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000))); sclk_table 1628 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (sclk_table->entries[i].clk/100) / 100000) * 1000 / sclk_table 1629 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000))); sclk_table 1632 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / sclk_table 1633 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); sclk_table 1635 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / sclk_table 1636 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); sclk_table 1640 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); sclk_table 885 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 888 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 906 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint8_t)dpm_table->sclk_table.count; sclk_table 908 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 910 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) sclk_table 919 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < dpm_table->sclk_table.count; i++) sclk_table 944 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 2; i < dpm_table->sclk_table.count; i++) sclk_table 1296 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { sclk_table 1299 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c hw_data->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 1383 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c result = phm_find_boot_level(&(data->dpm_table.sclk_table), sclk_table 1499 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1514 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 1516 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_table->entries[i].cks_enable << i; sclk_table 1517 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * sclk_table 1519 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); sclk_table 1520 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * sclk_table 1522 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (2522480 - sclk_table->entries[i].clk/100 * 115764/100)); sclk_table 1526 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_table->entries[i].cks_voffset) * 100 + 624) / 625); sclk_table 1582 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = sclk_table 1635 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c for (i = 0; i < sclk_table->count; i++) { sclk_table 1637 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625); sclk_table 1640 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c (sclk_table->entries[i].sclk_offset) / 100); sclk_table 2555 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { sclk_table 2558 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.sclk_table.dpm_levels[i].value, sclk_table 3289 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < dpm_table->sclk_table.count; i++) { sclk_table 3291 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->sclk_table.dpm_levels[i].value, sclk_table 3298 drivers/gpu/drm/radeon/ci_dpm.c if (i == (dpm_table->sclk_table.count - 1)) sclk_table 3304 drivers/gpu/drm/radeon/ci_dpm.c pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; sclk_table 3306 drivers/gpu/drm/radeon/ci_dpm.c ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); sclk_table 3464 drivers/gpu/drm/radeon/ci_dpm.c &pi->dpm_table.sclk_table, sclk_table 3479 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.sclk_table.count = 0; sclk_table 3482 drivers/gpu/drm/radeon/ci_dpm.c (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != sclk_table 3484 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = sclk_table 3486 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = sclk_table 3488 drivers/gpu/drm/radeon/ci_dpm.c pi->dpm_table.sclk_table.count++; sclk_table 3629 drivers/gpu/drm/radeon/ci_dpm.c ret = ci_find_boot_level(&pi->dpm_table.sclk_table, sclk_table 3765 drivers/gpu/drm/radeon/ci_dpm.c &pi->dpm_table.sclk_table, sclk_table 3860 drivers/gpu/drm/radeon/ci_dpm.c struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; sclk_table 3868 drivers/gpu/drm/radeon/ci_dpm.c for (i = 0; i < sclk_table->count; i++) { sclk_table 3869 drivers/gpu/drm/radeon/ci_dpm.c if (sclk == sclk_table->dpm_levels[i].value) sclk_table 3873 drivers/gpu/drm/radeon/ci_dpm.c if (i >= sclk_table->count) { sclk_table 3911 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; sclk_table 4179 drivers/gpu/drm/radeon/ci_dpm.c ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); sclk_table 69 drivers/gpu/drm/radeon/ci_dpm.h struct ci_single_dpm_table sclk_table;