sclk_setting 2641 drivers/gpu/drm/amd/include/atomfirmware.h struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; sclk_setting 842 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c uint32_t clock, SMU_SclkSetting *sclk_setting) sclk_setting 853 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->SclkFrequency = clock; sclk_setting 857 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw_int = dividers.usSclk_fcw_int; sclk_setting 858 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; sclk_setting 859 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; sclk_setting 860 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->PllRange = dividers.ucSclkPllRange; sclk_setting 861 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Sclk_slew_rate = 0x400; sclk_setting 862 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; sclk_setting 863 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Pcc_down_slew_rate = 0xffff; sclk_setting 864 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->SSc_En = dividers.ucSscEnable; sclk_setting 865 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; sclk_setting 866 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; sclk_setting 867 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; sclk_setting 876 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->PllRange = i; sclk_setting 881 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); sclk_setting 882 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; sclk_setting 885 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw_frac = temp & 0xffff; sclk_setting 889 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); sclk_setting 892 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->SSc_En = 0; sclk_setting 894 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->SSc_En = 1; sclk_setting 896 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); sclk_setting 897 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; sclk_setting 900 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw1_frac = temp & 0xffff; sclk_setting 717 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c uint32_t clock, SMU_SclkSetting *sclk_setting) sclk_setting 728 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->SclkFrequency = clock; sclk_setting 732 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw_int = dividers.usSclk_fcw_int; sclk_setting 733 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; sclk_setting 734 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; sclk_setting 735 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->PllRange = dividers.ucSclkPllRange; sclk_setting 736 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Sclk_slew_rate = 0x400; sclk_setting 737 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; sclk_setting 738 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Pcc_down_slew_rate = 0xffff; sclk_setting 739 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->SSc_En = dividers.ucSscEnable; sclk_setting 740 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; sclk_setting 741 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; sclk_setting 742 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac; sclk_setting 751 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->PllRange = i; sclk_setting 756 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw_int = (uint16_t) sclk_setting 757 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / sclk_setting 759 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; sclk_setting 762 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw_frac = temp & 0xffff; sclk_setting 766 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Pcc_fcw_int = (uint16_t) sclk_setting 767 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / sclk_setting 771 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->SSc_En = 0; sclk_setting 773 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->SSc_En = 1; sclk_setting 775 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw1_int = (uint16_t) sclk_setting 776 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / sclk_setting 778 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; sclk_setting 781 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->Fcw1_frac = temp & 0xffff;