sclk_mask        1572 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 	uint32_t sclk_mask, mclk_mask, soc_mask;
sclk_mask        1589 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 						 &sclk_mask,
sclk_mask        1594 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 		smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
sclk_mask        1291 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 				uint32_t *sclk_mask,
sclk_mask        1308 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 	*sclk_mask = 0;
sclk_mask        1315 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*sclk_mask = ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL;
sclk_mask        1321 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*sclk_mask = 0;
sclk_mask        1325 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 		*sclk_mask = gfx_dpm_table->count - 1;
sclk_mask        2728 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask)
sclk_mask        2759 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				*sclk_mask = count;
sclk_mask        2764 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			*sclk_mask = 0;
sclk_mask        2769 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
sclk_mask        2777 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				*sclk_mask = count;
sclk_mask        2782 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			*sclk_mask = 0;
sclk_mask        2787 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
sclk_mask        2806 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	uint32_t sclk_mask = 0;
sclk_mask        2811 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
sclk_mask        2827 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
sclk_mask        2830 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
sclk_mask        4032 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
sclk_mask        4040 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL;
sclk_mask        4048 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*sclk_mask = 0;
sclk_mask        4052 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*sclk_mask = table_info->vdd_dep_on_sclk->count - 1;
sclk_mask        4141 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	uint32_t sclk_mask = 0;
sclk_mask        4146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
sclk_mask        4162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
sclk_mask        4165 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
sclk_mask        1583 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
sclk_mask        1590 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	*sclk_mask = 0;
sclk_mask        1597 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
sclk_mask        1603 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*sclk_mask = 0;
sclk_mask        1607 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*sclk_mask = gfx_dpm_table->count - 1;
sclk_mask        1637 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	uint32_t sclk_mask = 0;
sclk_mask        1655 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
sclk_mask        1658 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
sclk_mask        2474 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
sclk_mask        2481 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*sclk_mask = 0;
sclk_mask        2488 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
sclk_mask        2494 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*sclk_mask = 0;
sclk_mask        2498 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*sclk_mask = gfx_dpm_table->count - 1;
sclk_mask        2673 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	uint32_t sclk_mask, mclk_mask, soc_mask;
sclk_mask        2692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
sclk_mask        2695 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
sclk_mask         442 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 				      uint32_t *sclk_mask,
sclk_mask         674 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \
sclk_mask         675 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	((smu)->ppt_funcs->get_profiling_clk_mask ? (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
sclk_mask        1214 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 					 uint32_t *sclk_mask,
sclk_mask        1222 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if (sclk_mask)
sclk_mask        1223 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*sclk_mask = 0;
sclk_mask        1228 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 		if(sclk_mask) {
sclk_mask        1232 drivers/gpu/drm/amd/powerplay/navi10_ppt.c 			*sclk_mask = level_count - 1;
sclk_mask        1988 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 			      uint32_t *sclk_mask,
sclk_mask        2004 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 	*sclk_mask = 0;
sclk_mask        2011 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL;
sclk_mask        2017 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*sclk_mask = 0;
sclk_mask        2021 drivers/gpu/drm/amd/powerplay/vega20_ppt.c 		*sclk_mask = gfx_dpm_table->count - 1;