sclk_dpm_enable_mask 2618 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
sclk_dpm_enable_mask 2620 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
sclk_dpm_enable_mask 2657 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
sclk_dpm_enable_mask 2660 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					data->dpm_level_enable_mask.sclk_dpm_enable_mask);
sclk_dpm_enable_mask 2695 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
sclk_dpm_enable_mask 2697 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 							      data->dpm_level_enable_mask.sclk_dpm_enable_mask);
sclk_dpm_enable_mask 3863 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask 4412 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);
sclk_dpm_enable_mask 4988 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) {
sclk_dpm_enable_mask 4990 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask;
sclk_dpm_enable_mask 4997 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
sclk_dpm_enable_mask  167 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h 	uint32_t  sclk_dpm_enable_mask;
sclk_dpm_enable_mask  177 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h 	uint32_t  sclk_dpm_enable_mask;
sclk_dpm_enable_mask  155 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h 	uint32_t  sclk_dpm_enable_mask;
sclk_dpm_enable_mask  208 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h 	uint32_t  sclk_dpm_enable_mask;
sclk_dpm_enable_mask  500 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask 1047 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask 1002 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask 1020 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask  732 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask  907 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask  912 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
sclk_dpm_enable_mask 3305 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask 3823 drivers/gpu/drm/radeon/ci_dpm.c 		if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
sclk_dpm_enable_mask 3826 drivers/gpu/drm/radeon/ci_dpm.c 								   pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
sclk_dpm_enable_mask 4178 drivers/gpu/drm/radeon/ci_dpm.c 	pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
sclk_dpm_enable_mask 4234 drivers/gpu/drm/radeon/ci_dpm.c 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
sclk_dpm_enable_mask 4236 drivers/gpu/drm/radeon/ci_dpm.c 			tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
sclk_dpm_enable_mask 4273 drivers/gpu/drm/radeon/ci_dpm.c 		    pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
sclk_dpm_enable_mask 4275 drivers/gpu/drm/radeon/ci_dpm.c 							     pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
sclk_dpm_enable_mask  111 drivers/gpu/drm/radeon/ci_dpm.h 	u32 sclk_dpm_enable_mask;