sclk 51 arch/mips/include/asm/txx9/generic.h unsigned int line, unsigned int sclk, int nocts); sclk 333 arch/mips/include/asm/txx9/tx3927.h void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask); sclk 264 arch/mips/include/asm/txx9/tx4927.h void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask); sclk 283 arch/mips/include/asm/txx9/tx4938.h void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask); sclk 504 arch/mips/include/asm/txx9/tx4939.h void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask); sclk 441 arch/mips/txx9/generic/setup.c unsigned int line, unsigned int sclk, int nocts) sclk 454 arch/mips/txx9/generic/setup.c if (sclk) { sclk 456 arch/mips/txx9/generic/setup.c req.uartclk = sclk; sclk 115 arch/mips/txx9/generic/setup_tx3927.c void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask) sclk 122 arch/mips/txx9/generic/setup_tx3927.c i, sclk, (1 << i) & cts_mask); sclk 231 arch/mips/txx9/generic/setup_tx4927.c void __init tx4927_sio_init(unsigned int sclk, unsigned int cts_mask) sclk 238 arch/mips/txx9/generic/setup_tx4927.c i, sclk, (1 << i) & cts_mask); sclk 288 arch/mips/txx9/generic/setup_tx4938.c void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) sclk 300 arch/mips/txx9/generic/setup_tx4938.c i, sclk, (1 << i) & cts_mask); sclk 298 arch/mips/txx9/generic/setup_tx4939.c void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask) sclk 316 arch/mips/txx9/generic/setup_tx4939.c i, sclk, (1 << i) & cts_mask); sclk 302 drivers/clk/clk-nomadik.c struct clk_src *sclk = to_src(hw); sclk 303 drivers/clk/clk-nomadik.c u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; sclk 304 drivers/clk/clk-nomadik.c u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; sclk 306 drivers/clk/clk-nomadik.c writel(sclk->clkbit, src_base + enreg); sclk 308 drivers/clk/clk-nomadik.c while (!(readl(src_base + sreg) & sclk->clkbit)) sclk 315 drivers/clk/clk-nomadik.c struct clk_src *sclk = to_src(hw); sclk 316 drivers/clk/clk-nomadik.c u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; sclk 317 drivers/clk/clk-nomadik.c u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; sclk 319 drivers/clk/clk-nomadik.c writel(sclk->clkbit, src_base + disreg); sclk 321 drivers/clk/clk-nomadik.c while (readl(src_base + sreg) & sclk->clkbit) sclk 327 drivers/clk/clk-nomadik.c struct clk_src *sclk = to_src(hw); sclk 328 drivers/clk/clk-nomadik.c u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; sclk 331 drivers/clk/clk-nomadik.c return !!(val & sclk->clkbit); sclk 353 drivers/clk/clk-nomadik.c struct clk_src *sclk; sclk 356 drivers/clk/clk-nomadik.c sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); sclk 357 drivers/clk/clk-nomadik.c if (!sclk) sclk 369 drivers/clk/clk-nomadik.c sclk->hw.init = &init; sclk 370 drivers/clk/clk-nomadik.c sclk->id = id; sclk 371 drivers/clk/clk-nomadik.c sclk->group1 = (id > 31); sclk 372 drivers/clk/clk-nomadik.c sclk->clkbit = BIT(id & 0x1f); sclk 375 drivers/clk/clk-nomadik.c name, id, sclk->group1, sclk->clkbit); sclk 377 drivers/clk/clk-nomadik.c ret = clk_hw_register(dev, &sclk->hw); sclk 379 drivers/clk/clk-nomadik.c kfree(sclk); sclk 383 drivers/clk/clk-nomadik.c return &sclk->hw; sclk 103 drivers/clk/clk-scmi.c static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) sclk 110 drivers/clk/clk-scmi.c .name = sclk->info->name, sclk 113 drivers/clk/clk-scmi.c sclk->hw.init = &init; sclk 114 drivers/clk/clk-scmi.c ret = devm_clk_hw_register(dev, &sclk->hw); sclk 116 drivers/clk/clk-scmi.c clk_hw_set_rate_range(&sclk->hw, sclk->info->range.min_rate, sclk 117 drivers/clk/clk-scmi.c sclk->info->range.max_rate); sclk 148 drivers/clk/clk-scmi.c struct scmi_clk *sclk; sclk 150 drivers/clk/clk-scmi.c sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); sclk 151 drivers/clk/clk-scmi.c if (!sclk) sclk 154 drivers/clk/clk-scmi.c sclk->info = handle->clk_ops->info_get(handle, idx); sclk 155 drivers/clk/clk-scmi.c if (!sclk->info) { sclk 160 drivers/clk/clk-scmi.c sclk->id = idx; sclk 161 drivers/clk/clk-scmi.c sclk->handle = handle; sclk 163 drivers/clk/clk-scmi.c err = scmi_clk_ops_init(dev, sclk); sclk 166 drivers/clk/clk-scmi.c devm_kfree(dev, sclk); sclk 169 drivers/clk/clk-scmi.c dev_dbg(dev, "Registered clock:%s\n", sclk->info->name); sclk 170 drivers/clk/clk-scmi.c hws[idx] = &sclk->hw; sclk 140 drivers/clk/clk-scpi.c struct scpi_clk *sclk, const char *name) sclk 150 drivers/clk/clk-scpi.c sclk->hw.init = &init; sclk 151 drivers/clk/clk-scpi.c sclk->scpi_ops = get_scpi_ops(); sclk 154 drivers/clk/clk-scpi.c sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id); sclk 155 drivers/clk/clk-scpi.c if (IS_ERR(sclk->info)) sclk 156 drivers/clk/clk-scpi.c return PTR_ERR(sclk->info); sclk 158 drivers/clk/clk-scpi.c if (sclk->scpi_ops->clk_get_range(sclk->id, &min, &max) || !max) sclk 164 drivers/clk/clk-scpi.c ret = devm_clk_hw_register(dev, &sclk->hw); sclk 166 drivers/clk/clk-scpi.c clk_hw_set_rate_range(&sclk->hw, min, max); sclk 178 drivers/clk/clk-scpi.c struct scpi_clk *sclk; sclk 183 drivers/clk/clk-scpi.c sclk = clk_data->clk[count]; sclk 184 drivers/clk/clk-scpi.c if (idx == sclk->id) sclk 185 drivers/clk/clk-scpi.c return &sclk->hw; sclk 214 drivers/clk/clk-scpi.c struct scpi_clk *sclk; sclk 218 drivers/clk/clk-scpi.c sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); sclk 219 drivers/clk/clk-scpi.c if (!sclk) sclk 234 drivers/clk/clk-scpi.c sclk->id = val; sclk 236 drivers/clk/clk-scpi.c err = scpi_clk_ops_init(dev, match, sclk, name); sclk 243 drivers/clk/clk-scpi.c clk_data->clk[idx] = sclk; sclk 455 drivers/clk/clk-u300.c static void syscon_block_reset_enable(struct clk_syscon *sclk) sclk 461 drivers/clk/clk-u300.c if (!sclk->res_reg) sclk 464 drivers/clk/clk-u300.c val = readw(sclk->res_reg); sclk 465 drivers/clk/clk-u300.c val |= BIT(sclk->res_bit); sclk 466 drivers/clk/clk-u300.c writew(val, sclk->res_reg); sclk 468 drivers/clk/clk-u300.c sclk->reset = true; sclk 471 drivers/clk/clk-u300.c static void syscon_block_reset_disable(struct clk_syscon *sclk) sclk 477 drivers/clk/clk-u300.c if (!sclk->res_reg) sclk 480 drivers/clk/clk-u300.c val = readw(sclk->res_reg); sclk 481 drivers/clk/clk-u300.c val &= ~BIT(sclk->res_bit); sclk 482 drivers/clk/clk-u300.c writew(val, sclk->res_reg); sclk 484 drivers/clk/clk-u300.c sclk->reset = false; sclk 489 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 492 drivers/clk/clk-u300.c if (sclk->reset) sclk 493 drivers/clk/clk-u300.c syscon_block_reset_disable(sclk); sclk 499 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 502 drivers/clk/clk-u300.c if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN) sclk 505 drivers/clk/clk-u300.c if (!sclk->reset) sclk 506 drivers/clk/clk-u300.c syscon_block_reset_enable(sclk); sclk 511 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 514 drivers/clk/clk-u300.c if (sclk->hw_ctrld) sclk 517 drivers/clk/clk-u300.c if (sclk->clk_val == 0xFFFFU) sclk 520 drivers/clk/clk-u300.c writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCER); sclk 526 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 529 drivers/clk/clk-u300.c if (sclk->hw_ctrld) sclk 531 drivers/clk/clk-u300.c if (sclk->clk_val == 0xFFFFU) sclk 534 drivers/clk/clk-u300.c if (sclk->clk_val == U300_SYSCON_SBCER_UART_CLK_EN) sclk 537 drivers/clk/clk-u300.c writew(sclk->clk_val, syscon_vbase + U300_SYSCON_SBCDR); sclk 542 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 546 drivers/clk/clk-u300.c if (!sclk->en_reg) sclk 549 drivers/clk/clk-u300.c val = readw(sclk->en_reg); sclk 550 drivers/clk/clk-u300.c val &= BIT(sclk->en_bit); sclk 568 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 571 drivers/clk/clk-u300.c switch (sclk->clk_val) { sclk 636 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 638 drivers/clk/clk-u300.c if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN) sclk 653 drivers/clk/clk-u300.c struct clk_syscon *sclk = to_syscon(hw); sclk 657 drivers/clk/clk-u300.c if (sclk->clk_val != U300_SYSCON_SBCER_CPU_CLK_EN) sclk 701 drivers/clk/clk-u300.c struct clk_syscon *sclk; sclk 705 drivers/clk/clk-u300.c sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); sclk 706 drivers/clk/clk-u300.c if (!sclk) sclk 714 drivers/clk/clk-u300.c sclk->hw.init = &init; sclk 715 drivers/clk/clk-u300.c sclk->hw_ctrld = hw_ctrld; sclk 717 drivers/clk/clk-u300.c sclk->reset = true; sclk 718 drivers/clk/clk-u300.c sclk->res_reg = res_reg; sclk 719 drivers/clk/clk-u300.c sclk->res_bit = res_bit; sclk 720 drivers/clk/clk-u300.c sclk->en_reg = en_reg; sclk 721 drivers/clk/clk-u300.c sclk->en_bit = en_bit; sclk 722 drivers/clk/clk-u300.c sclk->clk_val = clk_val; sclk 724 drivers/clk/clk-u300.c hw = &sclk->hw; sclk 727 drivers/clk/clk-u300.c kfree(sclk); sclk 34 drivers/clk/hisilicon/clkgate-separated.c struct clkgate_separated *sclk; sclk 38 drivers/clk/hisilicon/clkgate-separated.c sclk = container_of(hw, struct clkgate_separated, hw); sclk 39 drivers/clk/hisilicon/clkgate-separated.c if (sclk->lock) sclk 40 drivers/clk/hisilicon/clkgate-separated.c spin_lock_irqsave(sclk->lock, flags); sclk 41 drivers/clk/hisilicon/clkgate-separated.c reg = BIT(sclk->bit_idx); sclk 42 drivers/clk/hisilicon/clkgate-separated.c writel_relaxed(reg, sclk->enable); sclk 43 drivers/clk/hisilicon/clkgate-separated.c readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); sclk 44 drivers/clk/hisilicon/clkgate-separated.c if (sclk->lock) sclk 45 drivers/clk/hisilicon/clkgate-separated.c spin_unlock_irqrestore(sclk->lock, flags); sclk 51 drivers/clk/hisilicon/clkgate-separated.c struct clkgate_separated *sclk; sclk 55 drivers/clk/hisilicon/clkgate-separated.c sclk = container_of(hw, struct clkgate_separated, hw); sclk 56 drivers/clk/hisilicon/clkgate-separated.c if (sclk->lock) sclk 57 drivers/clk/hisilicon/clkgate-separated.c spin_lock_irqsave(sclk->lock, flags); sclk 58 drivers/clk/hisilicon/clkgate-separated.c reg = BIT(sclk->bit_idx); sclk 59 drivers/clk/hisilicon/clkgate-separated.c writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE); sclk 60 drivers/clk/hisilicon/clkgate-separated.c readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); sclk 61 drivers/clk/hisilicon/clkgate-separated.c if (sclk->lock) sclk 62 drivers/clk/hisilicon/clkgate-separated.c spin_unlock_irqrestore(sclk->lock, flags); sclk 67 drivers/clk/hisilicon/clkgate-separated.c struct clkgate_separated *sclk; sclk 70 drivers/clk/hisilicon/clkgate-separated.c sclk = container_of(hw, struct clkgate_separated, hw); sclk 71 drivers/clk/hisilicon/clkgate-separated.c reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); sclk 72 drivers/clk/hisilicon/clkgate-separated.c reg &= BIT(sclk->bit_idx); sclk 89 drivers/clk/hisilicon/clkgate-separated.c struct clkgate_separated *sclk; sclk 93 drivers/clk/hisilicon/clkgate-separated.c sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); sclk 94 drivers/clk/hisilicon/clkgate-separated.c if (!sclk) sclk 103 drivers/clk/hisilicon/clkgate-separated.c sclk->enable = reg + CLKGATE_SEPERATED_ENABLE; sclk 104 drivers/clk/hisilicon/clkgate-separated.c sclk->bit_idx = bit_idx; sclk 105 drivers/clk/hisilicon/clkgate-separated.c sclk->flags = clk_gate_flags; sclk 106 drivers/clk/hisilicon/clkgate-separated.c sclk->hw.init = &init; sclk 107 drivers/clk/hisilicon/clkgate-separated.c sclk->lock = lock; sclk 109 drivers/clk/hisilicon/clkgate-separated.c clk = clk_register(dev, &sclk->hw); sclk 111 drivers/clk/hisilicon/clkgate-separated.c kfree(sclk); sclk 31 drivers/clk/meson/sclk-div.c static int sclk_div_maxval(struct meson_sclk_div_data *sclk) sclk 33 drivers/clk/meson/sclk-div.c return (1 << sclk->div.width) - 1; sclk 36 drivers/clk/meson/sclk-div.c static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) sclk 38 drivers/clk/meson/sclk-div.c return sclk_div_maxval(sclk) + 1; sclk 51 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk) sclk 61 drivers/clk/meson/sclk-div.c maxdiv = sclk_div_maxdiv(sclk); sclk 92 drivers/clk/meson/sclk-div.c bestdiv = sclk_div_maxdiv(sclk); sclk 103 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 106 drivers/clk/meson/sclk-div.c div = sclk_div_bestdiv(hw, rate, prate, sclk); sclk 112 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk) sclk 114 drivers/clk/meson/sclk-div.c unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div * sclk 115 drivers/clk/meson/sclk-div.c sclk->cached_duty.num, sclk 116 drivers/clk/meson/sclk-div.c sclk->cached_duty.den); sclk 121 drivers/clk/meson/sclk-div.c meson_parm_write(clk->map, &sclk->hi, hi); sclk 128 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 130 drivers/clk/meson/sclk-div.c if (MESON_PARM_APPLICABLE(&sclk->hi)) { sclk 131 drivers/clk/meson/sclk-div.c memcpy(&sclk->cached_duty, duty, sizeof(*duty)); sclk 132 drivers/clk/meson/sclk-div.c sclk_apply_ratio(clk, sclk); sclk 142 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 145 drivers/clk/meson/sclk-div.c if (!MESON_PARM_APPLICABLE(&sclk->hi)) { sclk 151 drivers/clk/meson/sclk-div.c hi = meson_parm_read(clk->map, &sclk->hi); sclk 153 drivers/clk/meson/sclk-div.c duty->den = sclk->cached_div; sclk 158 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk) sclk 160 drivers/clk/meson/sclk-div.c if (MESON_PARM_APPLICABLE(&sclk->hi)) sclk 161 drivers/clk/meson/sclk-div.c sclk_apply_ratio(clk, sclk); sclk 163 drivers/clk/meson/sclk-div.c meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1); sclk 170 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 171 drivers/clk/meson/sclk-div.c unsigned long maxdiv = sclk_div_maxdiv(sclk); sclk 173 drivers/clk/meson/sclk-div.c sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv); sclk 176 drivers/clk/meson/sclk-div.c sclk_apply_divider(clk, sclk); sclk 185 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 187 drivers/clk/meson/sclk-div.c return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div); sclk 193 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 195 drivers/clk/meson/sclk-div.c sclk_apply_divider(clk, sclk); sclk 203 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 205 drivers/clk/meson/sclk-div.c meson_parm_write(clk->map, &sclk->div, 0); sclk 211 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 213 drivers/clk/meson/sclk-div.c if (meson_parm_read(clk->map, &sclk->div)) sclk 222 drivers/clk/meson/sclk-div.c struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); sclk 225 drivers/clk/meson/sclk-div.c val = meson_parm_read(clk->map, &sclk->div); sclk 229 drivers/clk/meson/sclk-div.c sclk->cached_div = sclk_div_maxdiv(sclk); sclk 231 drivers/clk/meson/sclk-div.c sclk->cached_div = val + 1; sclk 233 drivers/clk/meson/sclk-div.c sclk_div_get_duty_cycle(hw, &sclk->cached_duty); sclk 772 drivers/clk/microchip/clk-core.c struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); sclk 775 drivers/clk/microchip/clk-core.c div = (readl(sclk->slew_reg) >> SLEW_SYSDIV_SHIFT) & SLEW_SYSDIV; sclk 790 drivers/clk/microchip/clk-core.c struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); sclk 797 drivers/clk/microchip/clk-core.c spin_lock_irqsave(&sclk->core->reg_lock, flags); sclk 800 drivers/clk/microchip/clk-core.c v = readl(sclk->slew_reg); sclk 806 drivers/clk/microchip/clk-core.c writel(v, sclk->slew_reg); sclk 809 drivers/clk/microchip/clk-core.c err = readl_poll_timeout_atomic(sclk->slew_reg, v, sclk 812 drivers/clk/microchip/clk-core.c spin_unlock_irqrestore(&sclk->core->reg_lock, flags); sclk 819 drivers/clk/microchip/clk-core.c struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); sclk 822 drivers/clk/microchip/clk-core.c v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; sclk 824 drivers/clk/microchip/clk-core.c if (!sclk->parent_map) sclk 828 drivers/clk/microchip/clk-core.c if (sclk->parent_map[i] == v) sclk 835 drivers/clk/microchip/clk-core.c struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); sclk 840 drivers/clk/microchip/clk-core.c spin_lock_irqsave(&sclk->core->reg_lock, flags); sclk 843 drivers/clk/microchip/clk-core.c nosc = sclk->parent_map ? sclk->parent_map[index] : index; sclk 846 drivers/clk/microchip/clk-core.c v = readl(sclk->mux_reg); sclk 852 drivers/clk/microchip/clk-core.c writel(v, sclk->mux_reg); sclk 855 drivers/clk/microchip/clk-core.c writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); sclk 862 drivers/clk/microchip/clk-core.c err = readl_poll_timeout_atomic(sclk->slew_reg, v, sclk 865 drivers/clk/microchip/clk-core.c spin_unlock_irqrestore(&sclk->core->reg_lock, flags); sclk 873 drivers/clk/microchip/clk-core.c cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; sclk 885 drivers/clk/microchip/clk-core.c struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); sclk 893 drivers/clk/microchip/clk-core.c if (sclk->slew_div) { sclk 894 drivers/clk/microchip/clk-core.c spin_lock_irqsave(&sclk->core->reg_lock, flags); sclk 895 drivers/clk/microchip/clk-core.c v = readl(sclk->slew_reg); sclk 897 drivers/clk/microchip/clk-core.c v |= sclk->slew_div << SLEW_DIV_SHIFT; sclk 899 drivers/clk/microchip/clk-core.c writel(v, sclk->slew_reg); sclk 900 drivers/clk/microchip/clk-core.c spin_unlock_irqrestore(&sclk->core->reg_lock, flags); sclk 926 drivers/clk/microchip/clk-core.c struct pic32_sys_clk *sclk; sclk 929 drivers/clk/microchip/clk-core.c sclk = devm_kzalloc(core->dev, sizeof(*sclk), GFP_KERNEL); sclk 930 drivers/clk/microchip/clk-core.c if (!sclk) sclk 933 drivers/clk/microchip/clk-core.c sclk->core = core; sclk 934 drivers/clk/microchip/clk-core.c sclk->hw.init = &data->init_data; sclk 935 drivers/clk/microchip/clk-core.c sclk->mux_reg = data->mux_reg + core->iobase; sclk 936 drivers/clk/microchip/clk-core.c sclk->slew_reg = data->slew_reg + core->iobase; sclk 937 drivers/clk/microchip/clk-core.c sclk->slew_div = data->slew_div; sclk 938 drivers/clk/microchip/clk-core.c sclk->parent_map = data->parent_map; sclk 940 drivers/clk/microchip/clk-core.c clk = devm_clk_register(core->dev, &sclk->hw); sclk 186 drivers/clocksource/timer-atmel-st.c struct clk *sclk; sclk 217 drivers/clocksource/timer-atmel-st.c sclk = of_clk_get(node, 0); sclk 218 drivers/clocksource/timer-atmel-st.c if (IS_ERR(sclk)) { sclk 220 drivers/clocksource/timer-atmel-st.c return PTR_ERR(sclk); sclk 223 drivers/clocksource/timer-atmel-st.c ret = clk_prepare_enable(sclk); sclk 229 drivers/clocksource/timer-atmel-st.c sclk_rate = clk_get_rate(sclk); sclk 24 drivers/crypto/rockchip/rk3288_crypto.c err = clk_prepare_enable(dev->sclk); sclk 54 drivers/crypto/rockchip/rk3288_crypto.c clk_disable_unprepare(dev->sclk); sclk 64 drivers/crypto/rockchip/rk3288_crypto.c clk_disable_unprepare(dev->sclk); sclk 359 drivers/crypto/rockchip/rk3288_crypto.c crypto_info->sclk = devm_clk_get(&pdev->dev, "sclk"); sclk 360 drivers/crypto/rockchip/rk3288_crypto.c if (IS_ERR(crypto_info->sclk)) { sclk 361 drivers/crypto/rockchip/rk3288_crypto.c err = PTR_ERR(crypto_info->sclk); sclk 188 drivers/crypto/rockchip/rk3288_crypto.h struct clk *sclk; sclk 380 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = sclk 410 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = sclk 106 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h u32 sclk; sclk 112 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h u32 sclk; sclk 152 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h u32 sclk; sclk 771 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c vce_clk_table.entries[i].sclk = vce_state->sclk; sclk 2078 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c uint32_t sclk; sclk 2079 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c int r, size = sizeof(sclk); sclk 2088 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c (void *)&sclk, &size); sclk 2092 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c return snprintf(buf, PAGE_SIZE, "%d\n", sclk * 10 * 1000); sclk 692 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 sclk; /* engine clock in kHz */ sclk 776 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c fixed20_12 sclk, bandwidth; sclk 780 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c sclk.full = dfixed_const(wm->sclk); sclk 781 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c sclk.full = dfixed_div(sclk, a); sclk 786 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c bandwidth.full = dfixed_mul(a, sclk); sclk 1042 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c wm_high.sclk = sclk 1046 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c wm_high.sclk = adev->pm.current_sclk * 10; sclk 1081 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c wm_low.sclk = sclk 1085 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c wm_low.sclk = adev->pm.current_sclk * 10; sclk 718 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 sclk; /* engine clock in kHz */ sclk 802 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c fixed20_12 sclk, bandwidth; sclk 806 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c sclk.full = dfixed_const(wm->sclk); sclk 807 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c sclk.full = dfixed_div(sclk, a); sclk 812 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c bandwidth.full = dfixed_mul(a, sclk); sclk 1068 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c wm_high.sclk = sclk 1072 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c wm_high.sclk = adev->pm.current_sclk * 10; sclk 1107 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c wm_low.sclk = sclk 1111 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c wm_low.sclk = adev->pm.current_sclk * 10; sclk 491 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 sclk; /* engine clock in kHz */ sclk 575 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c fixed20_12 sclk, bandwidth; sclk 579 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c sclk.full = dfixed_const(wm->sclk); sclk 580 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c sclk.full = dfixed_div(sclk, a); sclk 585 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c bandwidth.full = dfixed_mul(a, sclk); sclk 850 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c wm_high.sclk = sclk 854 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c wm_high.sclk = adev->pm.current_sclk * 10; sclk 877 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c wm_low.sclk = sclk 881 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c wm_low.sclk = adev->pm.current_sclk * 10; sclk 627 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 sclk; /* engine clock in kHz */ sclk 711 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c fixed20_12 sclk, bandwidth; sclk 715 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c sclk.full = dfixed_const(wm->sclk); sclk 716 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c sclk.full = dfixed_div(sclk, a); sclk 721 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c bandwidth.full = dfixed_mul(a, sclk); sclk 977 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c wm_high.sclk = sclk 981 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c wm_high.sclk = adev->pm.current_sclk * 10; sclk 1016 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c wm_low.sclk = sclk 1020 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c wm_low.sclk = adev->pm.current_sclk * 10; sclk 662 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 index, u32 sclk) sclk 669 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk, false, ÷rs); sclk 674 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); sclk 807 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (table->entries[i].clk == pi->boot_pl.sclk) sclk 821 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) sclk 1782 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if ((table->entries[i].clk >= new_ps->levels[0].sclk) || sclk 1790 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) sclk 1796 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > sclk 1797 drivers/gpu/drm/amd/amdgpu/kv_dpm.c (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) sclk 1807 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || sclk 1816 drivers/gpu/drm/amd/amdgpu/kv_dpm.c new_ps->levels[new_ps->num_levels - 1].sclk) sclk 1822 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if ((new_ps->levels[0].sclk - sclk 1825 drivers/gpu/drm/amd/amdgpu/kv_dpm.c new_ps->levels[new_ps->num_levels -1].sclk)) sclk 2041 drivers/gpu/drm/amd/amdgpu/kv_dpm.c table->sclk = sclk 2097 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pi->boot_pl.sclk = pi->sys_info.bootup_sclk; sclk 2148 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk, u32 min_sclk_in_sr) sclk 2155 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (sclk < min) sclk 2162 drivers/gpu/drm/amd/amdgpu/kv_dpm.c temp = sclk >> i; sclk 2211 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk, mclk = 0; sclk 2229 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = min_sclk; sclk 2232 drivers/gpu/drm/amd/amdgpu/kv_dpm.c stable_p_state_sclk = (max_limits->sclk * 75) / 100; sclk 2244 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = stable_p_state_sclk; sclk 2248 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) sclk 2249 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; sclk 2255 drivers/gpu/drm/amd/amdgpu/kv_dpm.c if (ps->levels[i].sclk < sclk) sclk 2256 drivers/gpu/drm/amd/amdgpu/kv_dpm.c ps->levels[i].sclk = sclk; sclk 2265 drivers/gpu/drm/amd/amdgpu/kv_dpm.c ps->levels[i].sclk = table->entries[limit].clk; sclk 2277 drivers/gpu/drm/amd/amdgpu/kv_dpm.c ps->levels[i].sclk = table->entries[limit].sclk_frequency; sclk 2284 drivers/gpu/drm/amd/amdgpu/kv_dpm.c ps->levels[i].sclk = stable_p_state_sclk; sclk 2686 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk; sclk 2688 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 2689 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 2690 drivers/gpu/drm/amd/amdgpu/kv_dpm.c pl->sclk = sclk; sclk 2778 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk; sclk 2782 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 2783 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 2784 drivers/gpu/drm/amd/amdgpu/kv_dpm.c adev->pm.dpm.vce_states[i].sclk = sclk; sclk 2873 drivers/gpu/drm/amd/amdgpu/kv_dpm.c u32 sclk, tmp; sclk 2879 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); sclk 2887 drivers/gpu/drm/amd/amdgpu/kv_dpm.c current_index, sclk, vddc); sclk 2905 drivers/gpu/drm/amd/amdgpu/kv_dpm.c i, pl->sclk, sclk 2935 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return requested_state->levels[0].sclk; sclk 2937 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return requested_state->levels[requested_state->num_levels - 1].sclk; sclk 3231 drivers/gpu/drm/amd/amdgpu/kv_dpm.c return ((kv_cpl1->sclk == kv_cpl2->sclk) && sclk 3285 drivers/gpu/drm/amd/amdgpu/kv_dpm.c uint32_t sclk; sclk 3298 drivers/gpu/drm/amd/amdgpu/kv_dpm.c sclk = be32_to_cpu( sclk 3300 drivers/gpu/drm/amd/amdgpu/kv_dpm.c *((uint32_t *)value) = sclk; sclk 97 drivers/gpu/drm/amd/amdgpu/kv_dpm.h u32 sclk; sclk 1851 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SCLK_VALUE *sclk); sclk 2422 drivers/gpu/drm/amd/amdgpu/si_dpm.c prev_sclk = state->performance_levels[i-1].sclk; sclk 2423 drivers/gpu/drm/amd/amdgpu/si_dpm.c max_sclk = state->performance_levels[i].sclk; sclk 2441 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (min_sclk < state->performance_levels[0].sclk) sclk 2442 drivers/gpu/drm/amd/amdgpu/si_dpm.c min_sclk = state->performance_levels[0].sclk; sclk 2516 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && sclk 2954 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 sclk = 0; sclk 2967 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_calculate_sclk_params(adev, sclk, &sclk_params); sclk 2999 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk += 512; sclk 3183 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= sclk 3184 drivers/gpu/drm/amd/amdgpu/si_dpm.c current_state->performance_levels[current_state->performance_level_count - 1].sclk) sclk 3201 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < sclk 3202 drivers/gpu/drm/amd/amdgpu/si_dpm.c current_state->performance_levels[current_state->performance_level_count - 1].sclk) sclk 3292 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((pl->mclk == 0) || (pl->sclk == 0)) sclk 3295 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pl->mclk == pl->sclk) sclk 3298 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (pl->mclk > pl->sclk) { sclk 3299 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) sclk 3300 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk = btc_get_valid_sclk(adev, sclk 3301 drivers/gpu/drm/amd/amdgpu/si_dpm.c max_limits->sclk, sclk 3306 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) sclk 3309 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk - sclk 3434 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 mclk, sclk; sclk 3498 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ps->performance_levels[i].sclk > max_limits->sclk) sclk 3499 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[i].sclk = max_limits->sclk; sclk 3517 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ps->performance_levels[i].sclk > max_sclk_vddc) sclk 3518 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[i].sclk = max_sclk_vddc; sclk 3533 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ps->performance_levels[i].sclk > max_sclk) sclk 3534 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[i].sclk = max_sclk; sclk 3549 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; sclk 3552 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = ps->performance_levels[0].sclk; sclk 3557 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) sclk 3558 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; sclk 3564 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[0].sclk = sclk; sclk 3570 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = ps->performance_levels[0].sclk; sclk 3572 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (sclk < ps->performance_levels[i].sclk) sclk 3573 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = ps->performance_levels[i].sclk; sclk 3576 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[i].sclk = sclk; sclk 3581 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) sclk 3582 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; sclk 3615 drivers/gpu/drm/amd/amdgpu/si_dpm.c ps->performance_levels[i].sclk, sclk 4673 drivers/gpu/drm/amd/amdgpu/si_dpm.c u16 voltage, u32 sclk, u32 mclk, sclk 4680 drivers/gpu/drm/amd/amdgpu/si_dpm.c (sclk <= limits->entries[i].sclk) && sclk 4766 drivers/gpu/drm/amd/amdgpu/si_dpm.c (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); sclk 4769 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk, sclk 4863 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 4865 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 4867 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 4869 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = sclk 4871 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = sclk 4873 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = sclk 4876 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->initialState.levels[0].sclk.sclk_value = sclk 4877 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(initial_state->performance_levels[0].sclk); sclk 4910 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].sclk, sclk 5061 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 5063 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 5065 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 5067 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = sclk 5071 drivers/gpu/drm/amd/amdgpu/si_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 5246 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SCLK_VALUE *sclk) sclk 5303 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->sclk_value = engine_clock; sclk 5304 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; sclk 5305 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; sclk 5306 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; sclk 5307 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; sclk 5308 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; sclk 5309 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; sclk 5316 drivers/gpu/drm/amd/amdgpu/si_dpm.c SISLANDS_SMC_SCLK_VALUE *sclk) sclk 5323 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); sclk 5324 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); sclk 5325 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); sclk 5326 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); sclk 5327 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); sclk 5328 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); sclk 5329 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); sclk 5457 drivers/gpu/drm/amd/amdgpu/si_dpm.c ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); sclk 5500 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk, sclk 5534 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk, sclk 5574 drivers/gpu/drm/amd/amdgpu/si_dpm.c state->performance_levels[i + 1].sclk, sclk 5575 drivers/gpu/drm/amd/amdgpu/si_dpm.c state->performance_levels[i].sclk, sclk 5666 drivers/gpu/drm/amd/amdgpu/si_dpm.c threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; sclk 5700 drivers/gpu/drm/amd/amdgpu/si_dpm.c (state->performance_levels[i].sclk < threshold) ? sclk 7146 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); sclk 7147 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk |= clock_info->si.ucEngineClockHigh << 16; sclk 7193 drivers/gpu/drm/amd/amdgpu/si_dpm.c pl->sclk = adev->clock.default_sclk; sclk 7201 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; sclk 7290 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 sclk, mclk; sclk 7294 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = le16_to_cpu(clock_info->si.usEngineClockLow); sclk 7295 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk |= clock_info->si.ucEngineClockHigh << 16; sclk 7298 drivers/gpu/drm/amd/amdgpu/si_dpm.c adev->pm.dpm.vce_states[i].sclk = sclk; sclk 7459 drivers/gpu/drm/amd/amdgpu/si_dpm.c if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || sclk 7500 drivers/gpu/drm/amd/amdgpu/si_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); sclk 7877 drivers/gpu/drm/amd/amdgpu/si_dpm.c return requested_state->performance_levels[0].sclk; sclk 7879 drivers/gpu/drm/amd/amdgpu/si_dpm.c return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; sclk 7910 drivers/gpu/drm/amd/amdgpu/si_dpm.c i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); sclk 7913 drivers/gpu/drm/amd/amdgpu/si_dpm.c i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 7933 drivers/gpu/drm/amd/amdgpu/si_dpm.c (si_cpl1->sclk == si_cpl2->sclk) && sclk 7990 drivers/gpu/drm/amd/amdgpu/si_dpm.c uint32_t sclk, mclk; sclk 8002 drivers/gpu/drm/amd/amdgpu/si_dpm.c sclk = ps->performance_levels[pl_index].sclk; sclk 8003 drivers/gpu/drm/amd/amdgpu/si_dpm.c *((uint32_t *)value) = sclk; sclk 439 drivers/gpu/drm/amd/amdgpu/si_dpm.h RV770_SMC_SCLK_VALUE sclk; sclk 599 drivers/gpu/drm/amd/amdgpu/si_dpm.h u32 sclk; sclk 759 drivers/gpu/drm/amd/amdgpu/si_dpm.h NISLANDS_SMC_SCLK_VALUE sclk; sclk 153 drivers/gpu/drm/amd/amdgpu/sislands_smc.h SISLANDS_SMC_SCLK_VALUE sclk; sclk 102 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c struct bw_fixed sclk[8]; sclk 129 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_low] = vbios->low_sclk; sclk 130 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_mid1] = vbios->mid1_sclk; sclk 131 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_mid2] = vbios->mid2_sclk; sclk 132 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_mid3] = vbios->mid3_sclk; sclk 133 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_mid4] = vbios->mid4_sclk; sclk 134 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_mid5] = vbios->mid5_sclk; sclk 135 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_mid6] = vbios->mid6_sclk; sclk 136 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c sclk[s_high] = vbios->high_sclk; sclk 1188 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dmif_burst_time[i][j] = bw_max3(data->dmif_total_page_close_open_time, bw_div(data->total_display_reads_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_channels)))), bw_div(data->total_display_reads_required_data, (bw_mul(bw_mul(sclk[j], vbios->data_return_bus_width), bw_frc_to_fixed(dceip->percent_of_ideal_port_bw_received_after_urgent_latency, 100))))); sclk 1190 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->mcifwr_burst_time[i][j] = bw_max3(data->mcifwr_total_page_close_open_time, bw_div(data->total_display_writes_required_dram_access_data, (bw_mul(bw_div(bw_mul(bw_mul(data->dram_efficiency, yclk[i]), bw_int_to_fixed(vbios->dram_channel_width_in_bits)), bw_int_to_fixed(8)), bw_int_to_fixed(data->number_of_dram_wrchannels)))), bw_div(data->total_display_writes_required_data, (bw_mul(sclk[j], vbios->data_return_bus_width)))); sclk 1249 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_mul(bw_int_to_fixed(2), bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(bw_mul(data->bytes_per_request[i], data->pixel_rate[i]), data->scaler_limits_factor), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->dmif_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i])))))); sclk 1258 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->dram_speed_change_line_source_transfer_time[i][j][k] = bw_max2((bw_add((bw_div(data->src_data_for_first_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_first_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1)))))), (bw_add((bw_div(data->src_data_for_last_output_pixel[i], bw_min2(bw_mul(data->bytes_per_request[i], sclk[k]), bw_div(bw_mul(data->bytes_per_request[i], vbios->low_voltage_max_dispclk), bw_int_to_fixed(2))))), (bw_sub(bw_mul(data->mcifwr_burst_time[j][k], bw_floor2(bw_div(data->src_data_for_last_output_pixel[i], data->adjusted_data_buffer_size_in_memory[i]), bw_int_to_fixed(1))), data->active_time[i]))))); sclk 1582 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[low]),vbios->data_return_bus_width)) sclk 1583 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_low]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_low], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_low], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_low], vbios->low_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_low] == number_of_displays_enabled_with_margin))) { sclk 1588 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[mid]),vbios->data_return_bus_width)) sclk 1589 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_mid1]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid1], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid1], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid1], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid1] == number_of_displays_enabled_with_margin))) { sclk 1594 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid2]),vbios->data_return_bus_width)) sclk 1595 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_mid2]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid2], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid2], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid2], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid2] == number_of_displays_enabled_with_margin))) { sclk 1600 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid3]),vbios->data_return_bus_width)) sclk 1601 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_mid3]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid3], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid3], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid3], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid3] == number_of_displays_enabled_with_margin))) { sclk 1606 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid4]),vbios->data_return_bus_width)) sclk 1607 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_mid4]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid4], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid4], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid4], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid4] == number_of_displays_enabled_with_margin))) { sclk 1612 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid5]),vbios->data_return_bus_width)) sclk 1613 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_mid5]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid5], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid5], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid5], vbios->mid_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid5] == number_of_displays_enabled_with_margin))) { sclk 1618 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_mid6]),vbios->data_return_bus_width)) sclk 1619 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_mid6]) && (data->cpup_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (data->cpuc_state_change_enable == bw_def_no || (bw_mtn(data->blackout_duration_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->dispclk_required_for_blackout_duration[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && bw_ltn(data->dispclk_required_for_blackout_recovery[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk))) && (!data->increase_voltage_to_support_mclk_switch || data->nbp_state_change_enable == bw_def_no || (bw_mtn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(0)) && bw_ltn(data->min_dram_speed_change_margin[data->y_clk_level][s_mid6], bw_int_to_fixed(9999)) && bw_leq(data->dispclk_required_for_dram_speed_change[data->y_clk_level][s_mid6], vbios->high_voltage_max_dispclk) && data->num_displays_with_margin[data->y_clk_level][s_mid6] == number_of_displays_enabled_with_margin))) { sclk 1624 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_ltn(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width)) sclk 1625 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_high])) { sclk 1630 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c else if (bw_meq(data->total_average_bandwidth_no_compression, bw_mul(bw_mul(bw_frc_to_fixed(dceip->max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation, 100),sclk[s_high]),vbios->data_return_bus_width)) sclk 1631 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c && bw_ltn(data->required_sclk, sclk[s_high])) { sclk 1850 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->chunk_request_time = bw_add(data->chunk_request_time, (bw_div((bw_div(bw_int_to_fixed(pixels_per_chunk * data->bytes_per_pixel[i]), data->useful_bytes_per_request[i])), bw_min2(sclk[data->sclk_level], bw_div(data->dispclk, bw_int_to_fixed(2)))))); sclk 1854 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->cursor_request_time = (bw_div(data->cursor_total_data, (bw_mul(bw_int_to_fixed(32), sclk[data->sclk_level])))); sclk 1947 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->stutter_burst_time = bw_div(bw_int_to_fixed(data->total_stutter_dmif_buffer_size), bw_mul(sclk[data->sclk_level], vbios->data_return_bus_width)); sclk 63 drivers/gpu/drm/amd/display/dc/dm_services_types.h struct dm_pp_clock_range sclk; sclk 34 drivers/gpu/drm/amd/include/kgd_pp_interface.h u32 sclk; sclk 237 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || sclk 643 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t sclk, sclk 940 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c fSclk = GetScaledFraction(sclk, 100); sclk 1087 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t sclk, uint16_t virtual_voltage_Id, sclk 1101 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c cpu_to_le32(sclk); sclk 1339 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage) sclk 1348 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk); sclk 291 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); sclk 314 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); sclk 319 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); sclk 358 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c limits->sclk = le32_to_cpu(limitable->entries[0].ulSCLKLimit); sclk 824 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = sclk 825 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c pp_table_information->max_clock_voltage_on_dc.sclk; sclk 1261 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c vce_state->sclk = le32_to_cpu(sclk_dep_record->ulSclk); sclk 432 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) | sclk 1120 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c uint32_t sclk, mclk; sclk 1126 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c sclk = smum_get_argument(hwmgr); sclk 1128 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c *((uint32_t *)value) = sclk * 100; sclk 1700 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk = 0; sclk 1712 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c table_info->vddgfx_lookup_table, vv_id, &sclk)) { sclk 1718 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk_table->entries[j].clk == sclk && sclk 1720 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk += 5000; sclk 1726 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, sclk 1744 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c table_info->vddc_lookup_table, vv_id, &sclk)) { sclk 1752 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk_table->entries[j].clk == sclk && sclk 1754 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk += 5000; sclk 1762 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk, vv_id, &vddc) == 0) { sclk 2094 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c table_info->max_clock_voltage_on_ac.sclk = sclk 2103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; sclk 2479 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = sclk 2890 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk; sclk 2919 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) sclk 2920 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; sclk 2930 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c stable_pstate_sclk = (max_limits->sclk * 75) / 100; sclk 2964 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk = smu7_ps->performance_levels[0].engine_clock; sclk 2971 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk < minimum_clocks.engineClock) sclk 2972 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk = (minimum_clocks.engineClock > max_limits->sclk) ? sclk 2973 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c max_limits->sclk : minimum_clocks.engineClock; sclk 2979 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_ps->performance_levels[0].engine_clock = sclk; sclk 3528 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk, mclk, activity_percent; sclk 3539 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); sclk 3540 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c *((uint32_t *)value) = sclk; sclk 3600 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk = smu7_ps->performance_levels sclk 3609 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk == sclk_table->dpm_levels[i].value) sclk 3614 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (sclk > sclk_table->dpm_levels[i-1].value) { sclk 3616 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk_table->dpm_levels[i-1].value = sclk; sclk 3650 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c uint32_t sclk, max_sclk = 0; sclk 3655 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c sclk = smu7_ps->performance_levels[i].engine_clock; sclk 3656 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c if (max_sclk < sclk) sclk 3657 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c max_sclk = sclk; sclk 263 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c table->sclk = dep_table->entries[dep_table->count-1].clk; sclk 1481 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c info->engine_max_clock = limits->sclk; sclk 1690 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; sclk 1702 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c sclk = table->entries[sclk_index].clk; sclk 1703 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c *((uint32_t *)value) = sclk; sclk 461 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint16_t virtual_voltage_id, int32_t *sclk) sclk 482 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk; sclk 569 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t sclk, uint16_t id, uint16_t *voltage) sclk 577 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage); sclk 581 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol); sclk 89 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint16_t virtual_voltage_id, int32_t *sclk); sclk 95 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h uint32_t sclk, uint16_t id, uint16_t *voltage); sclk 557 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk = 0; sclk 568 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c table_info->vddc_lookup_table, vv_id, &sclk)) { sclk 571 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (socclk_table->entries[j].clk == sclk && sclk 573 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c sclk += 5000; sclk 580 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc), sclk 787 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c table_info->max_clock_voltage_on_ac.sclk = sclk 796 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = sclk 797 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c table_info->max_clock_voltage_on_ac.sclk; sclk 3137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk; sclk 3172 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c max_limits->sclk) sclk 3174 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c max_limits->sclk; sclk 3192 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c stable_pstate_sclk = (max_limits->sclk * sclk 3229 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c sclk = vega10_ps->performance_levels[0].gfx_clock; sclk 3232 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (sclk < minimum_clocks.engineClock) sclk 3233 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c sclk = (minimum_clocks.engineClock > max_limits->sclk) ? sclk 3234 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c max_limits->sclk : minimum_clocks.engineClock; sclk 3240 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c vega10_ps->performance_levels[0].gfx_clock = sclk; sclk 3291 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c uint32_t sclk = vega10_ps->performance_levels sclk 3299 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (sclk == sclk_table->dpm_levels[i].value) sclk 3304 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c if (sclk > sclk_table->dpm_levels[i-1].value) { sclk 3306 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c sclk_table->dpm_levels[i-1].value = sclk; sclk 4202 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c info->engine_max_clock = max_limits->sclk; sclk 863 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit); sclk 1023 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = sclk 1024 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c pp_table_info->max_clock_voltage_on_dc.sclk; sclk 1689 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c info->engine_max_clock = max_limits->sclk; sclk 2747 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c info->engine_max_clock = max_limits->sclk; sclk 511 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h uint32_t sclk; sclk 176 drivers/gpu/drm/amd/powerplay/inc/power_state.h unsigned long sclk; sclk 296 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk) sclk 359 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sclk->SclkFrequency = clock; sclk 360 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sclk->CgSpllFuncCntl3 = spll_func_cntl_3; sclk 361 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sclk->CgSpllFuncCntl4 = spll_func_cntl_4; sclk 362 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; sclk 363 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; sclk 364 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c sclk->SclkDid = (uint8_t)dividers.pll_post_divider; sclk 371 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c uint32_t sclk, uint32_t *p_shed) sclk 379 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c if (sclk < pl->entries[i].Sclk) { sclk 858 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) sclk 928 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk->SclkFrequency = clock; sclk 929 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk->CgSpllFuncCntl3 = spll_func_cntl_3; sclk 930 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk->CgSpllFuncCntl4 = spll_func_cntl_4; sclk 931 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; sclk 932 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; sclk 933 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c sclk->SclkDid = (uint8_t)dividers.pll_post_divider; sclk 796 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) sclk 863 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sclk->SclkFrequency = engine_clock; sclk 864 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sclk->CgSpllFuncCntl3 = spll_func_cntl_3; sclk 865 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sclk->CgSpllFuncCntl4 = spll_func_cntl_4; sclk 866 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; sclk 867 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; sclk 868 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c sclk->SclkDid = (uint8_t)dividers.pll_post_divider; sclk 875 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t sclk, uint32_t *p_shed) sclk 883 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c if (sclk < pl->entries[i].Sclk) { sclk 539 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) sclk 606 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk->SclkFrequency = engine_clock; sclk 607 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk->CgSpllFuncCntl3 = spll_func_cntl_3; sclk 608 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk->CgSpllFuncCntl4 = spll_func_cntl_4; sclk 609 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; sclk 610 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; sclk 611 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c sclk->SclkDid = (uint8_t)dividers.pll_post_divider; sclk 101 drivers/gpu/drm/armada/armada_510.c const struct drm_display_mode *mode, uint32_t *sclk) sclk 118 drivers/gpu/drm/armada/armada_510.c if (sclk) { sclk 121 drivers/gpu/drm/armada/armada_510.c *sclk = res.div | armada510_clk_sels[idx]; sclk 335 drivers/gpu/drm/armada/armada_crtc.c uint32_t lm, rm, tm, bm, val, sclk; sclk 351 drivers/gpu/drm/armada/armada_crtc.c dcrtc->variant->compute_clock(dcrtc, adj, &sclk); sclk 353 drivers/gpu/drm/armada/armada_crtc.c armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); sclk 67 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 sclk; sclk 75 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = device->crystal; sclk 79 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); sclk 82 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); sclk 88 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); sclk 94 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return sclk * N / M / P; sclk 102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 sclk, sctl, sdiv = 2; sclk 112 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_vco(clk, dsrc + (doff * 4)); sclk 126 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return (sclk * 2) / sdiv; sclk 138 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 sclk, sdiv; sclk 142 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_pll(clk, 0x137000 + (idx * 0x20)); sclk 144 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_pll(clk, 0x1370e0); sclk 147 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_div(clk, idx, 0x137160, 0x1371d0); sclk 152 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return (sclk * 2) / sdiv; sclk 154 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return sclk; sclk 223 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c u32 sclk; sclk 243 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = read_vco(clk, 0x137160 + (idx * 4)); sclk 245 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c sclk = calc_div(clk, idx, sclk, freq, ddiv); sclk 246 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c return sclk; sclk 68 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 sclk; sclk 77 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = device->crystal; sclk 81 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_pll(clk, 0x132020); sclk 85 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_div(clk, 0, 0x137320, 0x137330); sclk 92 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); sclk 101 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); sclk 102 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c return sclk / (M * P); sclk 121 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 sclk = read_vco(clk, dsrc + (doff * 4)); sclk 123 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c return (sclk * 2) / sdiv; sclk 149 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 sclk, sdiv; sclk 154 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_pll(clk, 0x137000 + (idx * 0x20)); sclk 157 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_div(clk, idx, 0x137160, 0x1371d0); sclk 163 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_div(clk, idx, 0x137160, 0x1371d0); sclk 166 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_pll(clk, 0x1370e0); sclk 172 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_div(clk, idx, 0x137160, 0x1371d0); sclk 182 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c return (sclk * 2) / sdiv; sclk 185 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c return sclk; sclk 236 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c u32 sclk; sclk 256 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = read_vco(clk, 0x137160 + (idx * 4)); sclk 258 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c sclk = calc_div(clk, idx, sclk, freq, ddiv); sclk 259 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c return sclk; sclk 64 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 sctl, sdiv, sclk; sclk 99 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c sclk = read_vco(clk, idx); sclk 101 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c return (sclk * 2) / sdiv; sclk 112 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 sclk = 0, P = 1, N = 1, M = 1; sclk 128 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c sclk = read_clk(clk, 0x00 + idx, false); sclk 131 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c sclk = read_clk(clk, 0x10 + idx, false); sclk 139 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c return sclk * N / MP; sclk 191 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c u32 oclk, sclk, sdiv; sclk 207 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c sclk = read_vco(clk, idx); sclk 208 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c sdiv = min((sclk * 2) / khz, (u32)65); sclk 209 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c oclk = (sclk * 2) / sdiv; sclk 216 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c oclk = (sclk * 2) / sdiv; sclk 150 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c int sclk = cstate->domain[nv_clk_src_shader]; sclk 169 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c if (sclk && sclk != gclk) { sclk 170 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c ret = nv40_clk_calc_pll(clk, 0x004008, sclk, sclk 1245 drivers/gpu/drm/radeon/btc_dpm.c u32 *sclk, u32 *mclk) sclk 1249 drivers/gpu/drm/radeon/btc_dpm.c if ((sclk == NULL) || (mclk == NULL)) sclk 1255 drivers/gpu/drm/radeon/btc_dpm.c if ((btc_blacklist_clocks[i].sclk == *sclk) && sclk 1262 drivers/gpu/drm/radeon/btc_dpm.c *sclk = btc_get_valid_sclk(rdev, max_sclk, *sclk + 1); sclk 1264 drivers/gpu/drm/radeon/btc_dpm.c if (*sclk < max_sclk) sclk 1265 drivers/gpu/drm/radeon/btc_dpm.c btc_skip_blacklist_clocks(rdev, max_sclk, max_mclk, sclk, mclk); sclk 1275 drivers/gpu/drm/radeon/btc_dpm.c if ((pl->mclk == 0) || (pl->sclk == 0)) sclk 1278 drivers/gpu/drm/radeon/btc_dpm.c if (pl->mclk == pl->sclk) sclk 1281 drivers/gpu/drm/radeon/btc_dpm.c if (pl->mclk > pl->sclk) { sclk 1282 drivers/gpu/drm/radeon/btc_dpm.c if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) sclk 1283 drivers/gpu/drm/radeon/btc_dpm.c pl->sclk = btc_get_valid_sclk(rdev, sclk 1284 drivers/gpu/drm/radeon/btc_dpm.c max_limits->sclk, sclk 1289 drivers/gpu/drm/radeon/btc_dpm.c if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) sclk 1292 drivers/gpu/drm/radeon/btc_dpm.c pl->sclk - sclk 1818 drivers/gpu/drm/radeon/btc_dpm.c ulv_pl->sclk, sclk 1821 drivers/gpu/drm/radeon/btc_dpm.c val = rv770_calculate_memory_refresh_rate(rdev, ulv_pl->sclk); sclk 1824 drivers/gpu/drm/radeon/btc_dpm.c val = cypress_calculate_burst_time(rdev, ulv_pl->sclk, ulv_pl->mclk); sclk 2102 drivers/gpu/drm/radeon/btc_dpm.c u32 mclk, sclk; sclk 2119 drivers/gpu/drm/radeon/btc_dpm.c if (ps->high.sclk > max_limits->sclk) sclk 2120 drivers/gpu/drm/radeon/btc_dpm.c ps->high.sclk = max_limits->sclk; sclk 2128 drivers/gpu/drm/radeon/btc_dpm.c if (ps->medium.sclk > max_limits->sclk) sclk 2129 drivers/gpu/drm/radeon/btc_dpm.c ps->medium.sclk = max_limits->sclk; sclk 2137 drivers/gpu/drm/radeon/btc_dpm.c if (ps->low.sclk > max_limits->sclk) sclk 2138 drivers/gpu/drm/radeon/btc_dpm.c ps->low.sclk = max_limits->sclk; sclk 2148 drivers/gpu/drm/radeon/btc_dpm.c sclk = ps->low.sclk; sclk 2153 drivers/gpu/drm/radeon/btc_dpm.c sclk = ps->low.sclk; sclk 2160 drivers/gpu/drm/radeon/btc_dpm.c ps->low.sclk = sclk; sclk 2165 drivers/gpu/drm/radeon/btc_dpm.c btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, sclk 2166 drivers/gpu/drm/radeon/btc_dpm.c &ps->low.sclk, &ps->low.mclk); sclk 2169 drivers/gpu/drm/radeon/btc_dpm.c if (ps->medium.sclk < ps->low.sclk) sclk 2170 drivers/gpu/drm/radeon/btc_dpm.c ps->medium.sclk = ps->low.sclk; sclk 2173 drivers/gpu/drm/radeon/btc_dpm.c if (ps->high.sclk < ps->medium.sclk) sclk 2174 drivers/gpu/drm/radeon/btc_dpm.c ps->high.sclk = ps->medium.sclk; sclk 2201 drivers/gpu/drm/radeon/btc_dpm.c btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, sclk 2202 drivers/gpu/drm/radeon/btc_dpm.c &ps->medium.sclk, &ps->medium.mclk); sclk 2203 drivers/gpu/drm/radeon/btc_dpm.c btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, sclk 2204 drivers/gpu/drm/radeon/btc_dpm.c &ps->high.sclk, &ps->high.mclk); sclk 2211 drivers/gpu/drm/radeon/btc_dpm.c ps->low.sclk, max_limits->vddc, &ps->low.vddc); sclk 2220 drivers/gpu/drm/radeon/btc_dpm.c ps->medium.sclk, max_limits->vddc, &ps->medium.vddc); sclk 2229 drivers/gpu/drm/radeon/btc_dpm.c ps->high.sclk, max_limits->vddc, &ps->high.vddc); sclk 2715 drivers/gpu/drm/radeon/btc_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || sclk 2758 drivers/gpu/drm/radeon/btc_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 2781 drivers/gpu/drm/radeon/btc_dpm.c return pl->sclk; sclk 2814 drivers/gpu/drm/radeon/btc_dpm.c return requested_state->low.sclk; sclk 2816 drivers/gpu/drm/radeon/btc_dpm.c return requested_state->high.sclk; sclk 46 drivers/gpu/drm/radeon/btc_dpm.h u32 *sclk, u32 *mclk); sclk 802 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk, mclk; sclk 833 drivers/gpu/drm/radeon/ci_dpm.c if (ps->performance_levels[i].sclk > max_limits->sclk) sclk 834 drivers/gpu/drm/radeon/ci_dpm.c ps->performance_levels[i].sclk = max_limits->sclk; sclk 842 drivers/gpu/drm/radeon/ci_dpm.c sclk = ps->performance_levels[0].sclk; sclk 845 drivers/gpu/drm/radeon/ci_dpm.c sclk = ps->performance_levels[0].sclk; sclk 849 drivers/gpu/drm/radeon/ci_dpm.c if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) sclk 850 drivers/gpu/drm/radeon/ci_dpm.c sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; sclk 855 drivers/gpu/drm/radeon/ci_dpm.c ps->performance_levels[0].sclk = sclk; sclk 858 drivers/gpu/drm/radeon/ci_dpm.c if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk) sclk 859 drivers/gpu/drm/radeon/ci_dpm.c ps->performance_levels[1].sclk = ps->performance_levels[0].sclk; sclk 2381 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk, sclk 2389 drivers/gpu/drm/radeon/ci_dpm.c if (sclk < limits->entries[i].sclk) { sclk 2453 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk, u32 min_sclk_in_sr) sclk 2460 drivers/gpu/drm/radeon/ci_dpm.c if (sclk < min) sclk 2464 drivers/gpu/drm/radeon/ci_dpm.c tmp = sclk / (1 << i); sclk 2523 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk, sclk 2531 drivers/gpu/drm/radeon/ci_dpm.c radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); sclk 2537 drivers/gpu/drm/radeon/ci_dpm.c ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2); sclk 2595 drivers/gpu/drm/radeon/ci_dpm.c boot_state->performance_levels[0].sclk) { sclk 3161 drivers/gpu/drm/radeon/ci_dpm.c SMU7_Discrete_GraphicsLevel *sclk) sclk 3205 drivers/gpu/drm/radeon/ci_dpm.c sclk->SclkFrequency = engine_clock; sclk 3206 drivers/gpu/drm/radeon/ci_dpm.c sclk->CgSpllFuncCntl3 = spll_func_cntl_3; sclk 3207 drivers/gpu/drm/radeon/ci_dpm.c sclk->CgSpllFuncCntl4 = spll_func_cntl_4; sclk 3208 drivers/gpu/drm/radeon/ci_dpm.c sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; sclk 3209 drivers/gpu/drm/radeon/ci_dpm.c sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; sclk 3210 drivers/gpu/drm/radeon/ci_dpm.c sclk->SclkDid = (u8)dividers.post_divider; sclk 3766 drivers/gpu/drm/radeon/ci_dpm.c state->performance_levels[0].sclk, sclk 3767 drivers/gpu/drm/radeon/ci_dpm.c state->performance_levels[high_limit_count].sclk); sclk 3861 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; sclk 3869 drivers/gpu/drm/radeon/ci_dpm.c if (sclk == sclk_table->dpm_levels[i].value) sclk 3902 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; sclk 3911 drivers/gpu/drm/radeon/ci_dpm.c dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk; sclk 4948 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = sclk 5484 drivers/gpu/drm/radeon/ci_dpm.c pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); sclk 5485 drivers/gpu/drm/radeon/ci_dpm.c pl->sclk |= clock_info->ci.ucEngineClockHigh << 16; sclk 5510 drivers/gpu/drm/radeon/ci_dpm.c pl->sclk = pi->vbios_boot_state.sclk_bootup_value; sclk 5620 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk, mclk; sclk 5624 drivers/gpu/drm/radeon/ci_dpm.c sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); sclk 5625 drivers/gpu/drm/radeon/ci_dpm.c sclk |= clock_info->ci.ucEngineClockHigh << 16; sclk 5628 drivers/gpu/drm/radeon/ci_dpm.c rdev->pm.dpm.vce_states[i].sclk = sclk; sclk 5932 drivers/gpu/drm/radeon/ci_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || sclk 5947 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk = ci_get_average_sclk_freq(rdev); sclk 5953 drivers/gpu/drm/radeon/ci_dpm.c sclk, mclk); sclk 5969 drivers/gpu/drm/radeon/ci_dpm.c i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane); sclk 5976 drivers/gpu/drm/radeon/ci_dpm.c u32 sclk = ci_get_average_sclk_freq(rdev); sclk 5978 drivers/gpu/drm/radeon/ci_dpm.c return sclk; sclk 5994 drivers/gpu/drm/radeon/ci_dpm.c return requested_state->performance_levels[0].sclk; sclk 5996 drivers/gpu/drm/radeon/ci_dpm.c return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; sclk 41 drivers/gpu/drm/radeon/ci_dpm.h u32 sclk; sclk 8922 drivers/gpu/drm/radeon/cik.c u32 sclk; /* engine clock in kHz */ sclk 9006 drivers/gpu/drm/radeon/cik.c fixed20_12 sclk, bandwidth; sclk 9010 drivers/gpu/drm/radeon/cik.c sclk.full = dfixed_const(wm->sclk); sclk 9011 drivers/gpu/drm/radeon/cik.c sclk.full = dfixed_div(sclk, a); sclk 9016 drivers/gpu/drm/radeon/cik.c bandwidth.full = dfixed_mul(a, sclk); sclk 9273 drivers/gpu/drm/radeon/cik.c wm_high.sclk = sclk 9277 drivers/gpu/drm/radeon/cik.c wm_high.sclk = rdev->pm.current_sclk * 10; sclk 9313 drivers/gpu/drm/radeon/cik.c wm_low.sclk = sclk 9317 drivers/gpu/drm/radeon/cik.c wm_low.sclk = rdev->pm.current_sclk * 10; sclk 692 drivers/gpu/drm/radeon/cypress_dpm.c ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk); sclk 726 drivers/gpu/drm/radeon/cypress_dpm.c pl->sclk, sclk 733 drivers/gpu/drm/radeon/cypress_dpm.c pl->sclk, sclk 934 drivers/gpu/drm/radeon/cypress_dpm.c new_state->low.sclk, sclk 937 drivers/gpu/drm/radeon/cypress_dpm.c new_state->medium.sclk, sclk 940 drivers/gpu/drm/radeon/cypress_dpm.c new_state->high.sclk, sclk 1265 drivers/gpu/drm/radeon/cypress_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 1267 drivers/gpu/drm/radeon/cypress_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 1269 drivers/gpu/drm/radeon/cypress_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 1271 drivers/gpu/drm/radeon/cypress_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = sclk 1273 drivers/gpu/drm/radeon/cypress_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = sclk 1276 drivers/gpu/drm/radeon/cypress_dpm.c table->initialState.levels[0].sclk.sclk_value = sclk 1277 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be32(initial_state->low.sclk); sclk 1448 drivers/gpu/drm/radeon/cypress_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 1450 drivers/gpu/drm/radeon/cypress_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 1452 drivers/gpu/drm/radeon/cypress_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 1455 drivers/gpu/drm/radeon/cypress_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 1934 drivers/gpu/drm/radeon/evergreen.c u32 sclk; /* engine clock in kHz */ sclk 1991 drivers/gpu/drm/radeon/evergreen.c fixed20_12 sclk, bandwidth; sclk 1995 drivers/gpu/drm/radeon/evergreen.c sclk.full = dfixed_const(wm->sclk); sclk 1996 drivers/gpu/drm/radeon/evergreen.c sclk.full = dfixed_div(sclk, a); sclk 2001 drivers/gpu/drm/radeon/evergreen.c bandwidth.full = dfixed_mul(a, sclk); sclk 2183 drivers/gpu/drm/radeon/evergreen.c wm_high.sclk = sclk 2187 drivers/gpu/drm/radeon/evergreen.c wm_high.sclk = rdev->pm.current_sclk * 10; sclk 2210 drivers/gpu/drm/radeon/evergreen.c wm_low.sclk = sclk 2214 drivers/gpu/drm/radeon/evergreen.c wm_low.sclk = rdev->pm.current_sclk * 10; sclk 536 drivers/gpu/drm/radeon/kv_dpm.c u32 index, u32 sclk) sclk 543 drivers/gpu/drm/radeon/kv_dpm.c sclk, false, ÷rs); sclk 548 drivers/gpu/drm/radeon/kv_dpm.c pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); sclk 725 drivers/gpu/drm/radeon/kv_dpm.c if (table->entries[i].clk == pi->boot_pl.sclk) sclk 739 drivers/gpu/drm/radeon/kv_dpm.c if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) sclk 1718 drivers/gpu/drm/radeon/kv_dpm.c if ((table->entries[i].clk >= new_ps->levels[0].sclk) || sclk 1726 drivers/gpu/drm/radeon/kv_dpm.c if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) sclk 1732 drivers/gpu/drm/radeon/kv_dpm.c if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > sclk 1733 drivers/gpu/drm/radeon/kv_dpm.c (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) sclk 1743 drivers/gpu/drm/radeon/kv_dpm.c if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || sclk 1752 drivers/gpu/drm/radeon/kv_dpm.c new_ps->levels[new_ps->num_levels - 1].sclk) sclk 1758 drivers/gpu/drm/radeon/kv_dpm.c if ((new_ps->levels[0].sclk - sclk 1761 drivers/gpu/drm/radeon/kv_dpm.c new_ps->levels[new_ps->num_levels -1].sclk)) sclk 1975 drivers/gpu/drm/radeon/kv_dpm.c table->sclk = sclk 2031 drivers/gpu/drm/radeon/kv_dpm.c pi->boot_pl.sclk = pi->sys_info.bootup_sclk; sclk 2082 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk, u32 min_sclk_in_sr) sclk 2090 drivers/gpu/drm/radeon/kv_dpm.c if (sclk < min) sclk 2097 drivers/gpu/drm/radeon/kv_dpm.c temp = sclk / sumo_get_sleep_divider_from_id(i); sclk 2146 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk, mclk = 0; sclk 2164 drivers/gpu/drm/radeon/kv_dpm.c sclk = min_sclk; sclk 2167 drivers/gpu/drm/radeon/kv_dpm.c stable_p_state_sclk = (max_limits->sclk * 75) / 100; sclk 2179 drivers/gpu/drm/radeon/kv_dpm.c sclk = stable_p_state_sclk; sclk 2183 drivers/gpu/drm/radeon/kv_dpm.c if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) sclk 2184 drivers/gpu/drm/radeon/kv_dpm.c sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; sclk 2190 drivers/gpu/drm/radeon/kv_dpm.c if (ps->levels[i].sclk < sclk) sclk 2191 drivers/gpu/drm/radeon/kv_dpm.c ps->levels[i].sclk = sclk; sclk 2200 drivers/gpu/drm/radeon/kv_dpm.c ps->levels[i].sclk = table->entries[limit].clk; sclk 2212 drivers/gpu/drm/radeon/kv_dpm.c ps->levels[i].sclk = table->entries[limit].sclk_frequency; sclk 2219 drivers/gpu/drm/radeon/kv_dpm.c ps->levels[i].sclk = stable_p_state_sclk; sclk 2618 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk; sclk 2620 drivers/gpu/drm/radeon/kv_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 2621 drivers/gpu/drm/radeon/kv_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 2622 drivers/gpu/drm/radeon/kv_dpm.c pl->sclk = sclk; sclk 2710 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk; sclk 2714 drivers/gpu/drm/radeon/kv_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 2715 drivers/gpu/drm/radeon/kv_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 2716 drivers/gpu/drm/radeon/kv_dpm.c rdev->pm.dpm.vce_states[i].sclk = sclk; sclk 2809 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk, tmp; sclk 2815 drivers/gpu/drm/radeon/kv_dpm.c sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); sclk 2822 drivers/gpu/drm/radeon/kv_dpm.c current_index, sclk, vddc); sclk 2832 drivers/gpu/drm/radeon/kv_dpm.c u32 sclk; sclk 2837 drivers/gpu/drm/radeon/kv_dpm.c sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); sclk 2838 drivers/gpu/drm/radeon/kv_dpm.c return sclk; sclk 2861 drivers/gpu/drm/radeon/kv_dpm.c i, pl->sclk, sclk 2890 drivers/gpu/drm/radeon/kv_dpm.c return requested_state->levels[0].sclk; sclk 2892 drivers/gpu/drm/radeon/kv_dpm.c return requested_state->levels[requested_state->num_levels - 1].sclk; sclk 71 drivers/gpu/drm/radeon/kv_dpm.h u32 sclk; sclk 812 drivers/gpu/drm/radeon/ni_dpm.c if (ps->performance_levels[i].sclk > max_limits->sclk) sclk 813 drivers/gpu/drm/radeon/ni_dpm.c ps->performance_levels[i].sclk = max_limits->sclk; sclk 831 drivers/gpu/drm/radeon/ni_dpm.c btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, sclk 832 drivers/gpu/drm/radeon/ni_dpm.c &ps->performance_levels[0].sclk, sclk 836 drivers/gpu/drm/radeon/ni_dpm.c if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) sclk 837 drivers/gpu/drm/radeon/ni_dpm.c ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; sclk 866 drivers/gpu/drm/radeon/ni_dpm.c btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk, sclk 867 drivers/gpu/drm/radeon/ni_dpm.c &ps->performance_levels[i].sclk, sclk 876 drivers/gpu/drm/radeon/ni_dpm.c ps->performance_levels[i].sclk, sclk 1623 drivers/gpu/drm/radeon/ni_dpm.c (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk); sclk 1626 drivers/gpu/drm/radeon/ni_dpm.c radeon_atom_set_engine_dram_timings(rdev, pl->sclk, pl->mclk); sclk 1711 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 1713 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 1715 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 1717 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = sclk 1719 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = sclk 1721 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = sclk 1723 drivers/gpu/drm/radeon/ni_dpm.c table->initialState.levels[0].sclk.sclk_value = sclk 1724 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be32(initial_state->performance_levels[0].sclk); sclk 1914 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 1915 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 1916 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 1917 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4); sclk 1919 drivers/gpu/drm/radeon/ni_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 2000 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SCLK_VALUE *sclk) sclk 2058 drivers/gpu/drm/radeon/ni_dpm.c sclk->sclk_value = engine_clock; sclk 2059 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; sclk 2060 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; sclk 2061 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; sclk 2062 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; sclk 2063 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; sclk 2064 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; sclk 2071 drivers/gpu/drm/radeon/ni_dpm.c NISLANDS_SMC_SCLK_VALUE *sclk) sclk 2078 drivers/gpu/drm/radeon/ni_dpm.c sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); sclk 2079 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); sclk 2080 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); sclk 2081 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); sclk 2082 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); sclk 2083 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); sclk 2084 drivers/gpu/drm/radeon/ni_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); sclk 2100 drivers/gpu/drm/radeon/ni_dpm.c u32 sclk = 0; sclk 2112 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params); sclk 2148 drivers/gpu/drm/radeon/ni_dpm.c sclk += 512; sclk 2324 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk); sclk 2356 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, sclk 2361 drivers/gpu/drm/radeon/ni_dpm.c ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1); sclk 2418 drivers/gpu/drm/radeon/ni_dpm.c state->performance_levels[i + 1].sclk, sclk 2419 drivers/gpu/drm/radeon/ni_dpm.c state->performance_levels[i].sclk, sclk 2426 drivers/gpu/drm/radeon/ni_dpm.c state->performance_levels[i + 1].sclk, sclk 2427 drivers/gpu/drm/radeon/ni_dpm.c state->performance_levels[i].sclk, sclk 2502 drivers/gpu/drm/radeon/ni_dpm.c prev_sclk = state->performance_levels[i-1].sclk; sclk 2503 drivers/gpu/drm/radeon/ni_dpm.c max_sclk = state->performance_levels[i].sclk; sclk 2517 drivers/gpu/drm/radeon/ni_dpm.c if (min_sclk < state->performance_levels[0].sclk) sclk 2518 drivers/gpu/drm/radeon/ni_dpm.c min_sclk = state->performance_levels[0].sclk; sclk 2575 drivers/gpu/drm/radeon/ni_dpm.c if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && sclk 2632 drivers/gpu/drm/radeon/ni_dpm.c u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100; sclk 2653 drivers/gpu/drm/radeon/ni_dpm.c (state->performance_levels[i].sclk < threshold) ? sclk 3519 drivers/gpu/drm/radeon/ni_dpm.c if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= sclk 3520 drivers/gpu/drm/radeon/ni_dpm.c current_state->performance_levels[current_state->performance_level_count - 1].sclk) sclk 3537 drivers/gpu/drm/radeon/ni_dpm.c if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < sclk 3538 drivers/gpu/drm/radeon/ni_dpm.c current_state->performance_levels[current_state->performance_level_count - 1].sclk) sclk 3931 drivers/gpu/drm/radeon/ni_dpm.c pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); sclk 3932 drivers/gpu/drm/radeon/ni_dpm.c pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16; sclk 3971 drivers/gpu/drm/radeon/ni_dpm.c pl->sclk = rdev->clock.default_sclk; sclk 3978 drivers/gpu/drm/radeon/ni_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; sclk 4261 drivers/gpu/drm/radeon/ni_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || sclk 4296 drivers/gpu/drm/radeon/ni_dpm.c i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); sclk 4299 drivers/gpu/drm/radeon/ni_dpm.c i, pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 4321 drivers/gpu/drm/radeon/ni_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 4339 drivers/gpu/drm/radeon/ni_dpm.c return pl->sclk; sclk 4367 drivers/gpu/drm/radeon/ni_dpm.c return requested_state->performance_levels[0].sclk; sclk 4369 drivers/gpu/drm/radeon/ni_dpm.c return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; sclk 108 drivers/gpu/drm/radeon/nislands_smc.h NISLANDS_SMC_SCLK_VALUE sclk; sclk 288 drivers/gpu/drm/radeon/r100.c clock_info[rdev->pm.requested_clock_mode_index].sclk, sclk 3261 drivers/gpu/drm/radeon/r100.c sclk_ff = rdev->pm.sclk; sclk 528 drivers/gpu/drm/radeon/r600.c clock_info[rdev->pm.requested_clock_mode_index].sclk, sclk 973 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = sclk 1003 drivers/gpu/drm/radeon/r600_dpm.c rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = sclk 1281 drivers/gpu/drm/radeon/radeon.h u32 sclk; sclk 1368 drivers/gpu/drm/radeon/radeon.h u32 sclk; sclk 1374 drivers/gpu/drm/radeon/radeon.h u32 sclk; sclk 1414 drivers/gpu/drm/radeon/radeon.h u32 sclk; sclk 1528 drivers/gpu/drm/radeon/radeon.h u32 sclk; sclk 1605 drivers/gpu/drm/radeon/radeon.h fixed20_12 sclk; sclk 2150 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[0].sclk = sclk 2154 drivers/gpu/drm/radeon/radeon_atombios.c (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) sclk 2185 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[0].sclk = sclk 2189 drivers/gpu/drm/radeon/radeon_atombios.c (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) sclk 2221 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[0].sclk = sclk 2225 drivers/gpu/drm/radeon/radeon_atombios.c (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) sclk 2449 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; sclk 2464 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[j].sclk = sclk 2481 drivers/gpu/drm/radeon/radeon_atombios.c u32 sclk, mclk; sclk 2486 drivers/gpu/drm/radeon/radeon_atombios.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 2487 drivers/gpu/drm/radeon/radeon_atombios.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 2488 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; sclk 2490 drivers/gpu/drm/radeon/radeon_atombios.c sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); sclk 2491 drivers/gpu/drm/radeon/radeon_atombios.c sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; sclk 2492 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; sclk 2495 drivers/gpu/drm/radeon/radeon_atombios.c sclk = le16_to_cpu(clock_info->ci.usEngineClockLow); sclk 2496 drivers/gpu/drm/radeon/radeon_atombios.c sclk |= clock_info->ci.ucEngineClockHigh << 16; sclk 2500 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; sclk 2504 drivers/gpu/drm/radeon/radeon_atombios.c sclk = le16_to_cpu(clock_info->si.usEngineClockLow); sclk 2505 drivers/gpu/drm/radeon/radeon_atombios.c sclk |= clock_info->si.ucEngineClockHigh << 16; sclk 2509 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; sclk 2517 drivers/gpu/drm/radeon/radeon_atombios.c sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); sclk 2518 drivers/gpu/drm/radeon/radeon_atombios.c sclk |= clock_info->evergreen.ucEngineClockHigh << 16; sclk 2522 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; sclk 2530 drivers/gpu/drm/radeon/radeon_atombios.c sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); sclk 2531 drivers/gpu/drm/radeon/radeon_atombios.c sclk |= clock_info->r600.ucEngineClockHigh << 16; sclk 2535 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; sclk 2563 drivers/gpu/drm/radeon/radeon_atombios.c if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0) sclk 2568 drivers/gpu/drm/radeon/radeon_atombios.c (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)) sclk 2636 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[0].sclk = sclk 2732 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[0].sclk = sclk 2804 drivers/gpu/drm/radeon/radeon_atombios.c rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; sclk 42 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, sclk; sclk 55 drivers/gpu/drm/radeon/radeon_clocks.c sclk = fb_div / ref_div; sclk 59 drivers/gpu/drm/radeon/radeon_clocks.c sclk >>= 1; sclk 61 drivers/gpu/drm/radeon/radeon_clocks.c sclk >>= 2; sclk 63 drivers/gpu/drm/radeon/radeon_clocks.c sclk >>= 3; sclk 65 drivers/gpu/drm/radeon/radeon_clocks.c return sclk; sclk 741 drivers/gpu/drm/radeon/radeon_combios.c uint16_t sclk, mclk; sclk 795 drivers/gpu/drm/radeon/radeon_combios.c sclk = RBIOS16(pll_info + 0xa); sclk 797 drivers/gpu/drm/radeon/radeon_combios.c if (sclk == 0) sclk 798 drivers/gpu/drm/radeon/radeon_combios.c sclk = 200 * 100; sclk 802 drivers/gpu/drm/radeon/radeon_combios.c rdev->clock.default_sclk = sclk; sclk 2738 drivers/gpu/drm/radeon/radeon_combios.c rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); sclk 2740 drivers/gpu/drm/radeon/radeon_combios.c (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) sclk 2812 drivers/gpu/drm/radeon/radeon_combios.c rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; sclk 726 drivers/gpu/drm/radeon/radeon_device.c u32 sclk = rdev->pm.current_sclk; sclk 731 drivers/gpu/drm/radeon/radeon_device.c rdev->pm.sclk.full = dfixed_const(sclk); sclk 732 drivers/gpu/drm/radeon/radeon_device.c rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); sclk 739 drivers/gpu/drm/radeon/radeon_device.c rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); sclk 241 drivers/gpu/drm/radeon/radeon_i2c.c u32 sclk = rdev->pm.current_sclk; sclk 261 drivers/gpu/drm/radeon/radeon_i2c.c nm = (sclk * 10) / (i2c_clock * 4); sclk 276 drivers/gpu/drm/radeon/radeon_i2c.c prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; sclk 291 drivers/gpu/drm/radeon/radeon_i2c.c prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); sclk 293 drivers/gpu/drm/radeon/radeon_i2c.c prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; sclk 520 drivers/gpu/drm/radeon/radeon_kms.c *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; sclk 174 drivers/gpu/drm/radeon/radeon_pm.c u32 sclk, mclk; sclk 182 drivers/gpu/drm/radeon/radeon_pm.c sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. sclk 183 drivers/gpu/drm/radeon/radeon_pm.c clock_info[rdev->pm.requested_clock_mode_index].sclk; sclk 184 drivers/gpu/drm/radeon/radeon_pm.c if (sclk > rdev->pm.default_sclk) sclk 185 drivers/gpu/drm/radeon/radeon_pm.c sclk = rdev->pm.default_sclk; sclk 206 drivers/gpu/drm/radeon/radeon_pm.c if (sclk < rdev->pm.current_sclk) sclk 223 drivers/gpu/drm/radeon/radeon_pm.c if (sclk != rdev->pm.current_sclk) { sclk 225 drivers/gpu/drm/radeon/radeon_pm.c radeon_set_engine_clock(rdev, sclk); sclk 227 drivers/gpu/drm/radeon/radeon_pm.c rdev->pm.current_sclk = sclk; sclk 228 drivers/gpu/drm/radeon/radeon_pm.c DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); sclk 344 drivers/gpu/drm/radeon/radeon_pm.c clock_info->sclk * 10); sclk 348 drivers/gpu/drm/radeon/radeon_pm.c clock_info->sclk * 10, sclk 269 drivers/gpu/drm/radeon/rs690.c fixed20_12 sclk; sclk 281 drivers/gpu/drm/radeon/rs690.c fixed20_12 sclk, core_bandwidth, max_bandwidth; sclk 298 drivers/gpu/drm/radeon/rs690.c sclk.full = dfixed_const(selected_sclk); sclk 299 drivers/gpu/drm/radeon/rs690.c sclk.full = dfixed_div(sclk, a); sclk 303 drivers/gpu/drm/radeon/rs690.c core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); sclk 387 drivers/gpu/drm/radeon/rs690.c sclk.full = dfixed_mul(max_bandwidth, a); sclk 389 drivers/gpu/drm/radeon/rs690.c sclk.full = dfixed_div(a, sclk); sclk 396 drivers/gpu/drm/radeon/rs690.c chunk_time.full = dfixed_mul(sclk, a); sclk 484 drivers/gpu/drm/radeon/rs690.c fill_rate.full = dfixed_div(wm0->sclk, a); sclk 532 drivers/gpu/drm/radeon/rs690.c fill_rate.full = dfixed_div(wm0->sclk, a); sclk 559 drivers/gpu/drm/radeon/rs690.c fill_rate.full = dfixed_div(wm1->sclk, a); sclk 754 drivers/gpu/drm/radeon/rs780_dpm.c u32 sclk; sclk 756 drivers/gpu/drm/radeon/rs780_dpm.c sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow); sclk 757 drivers/gpu/drm/radeon/rs780_dpm.c sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; sclk 758 drivers/gpu/drm/radeon/rs780_dpm.c ps->sclk_low = sclk; sclk 759 drivers/gpu/drm/radeon/rs780_dpm.c sclk = le16_to_cpu(clock_info->rs780.usHighEngineClockLow); sclk 760 drivers/gpu/drm/radeon/rs780_dpm.c sclk |= clock_info->rs780.ucHighEngineClockHigh << 16; sclk 761 drivers/gpu/drm/radeon/rs780_dpm.c ps->sclk_high = sclk; sclk 993 drivers/gpu/drm/radeon/rs780_dpm.c u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / sclk 999 drivers/gpu/drm/radeon/rs780_dpm.c if (sclk < (ps->sclk_low + 500)) sclk 1015 drivers/gpu/drm/radeon/rs780_dpm.c u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / sclk 1018 drivers/gpu/drm/radeon/rs780_dpm.c return sclk; sclk 952 drivers/gpu/drm/radeon/rv515.c fixed20_12 sclk; sclk 964 drivers/gpu/drm/radeon/rv515.c fixed20_12 sclk; sclk 982 drivers/gpu/drm/radeon/rv515.c sclk.full = dfixed_const(selected_sclk); sclk 983 drivers/gpu/drm/radeon/rv515.c sclk.full = dfixed_div(sclk, a); sclk 1050 drivers/gpu/drm/radeon/rv515.c chunk_time.full = dfixed_div(a, sclk); sclk 1135 drivers/gpu/drm/radeon/rv515.c fill_rate.full = dfixed_div(wm0->sclk, a); sclk 1183 drivers/gpu/drm/radeon/rv515.c fill_rate.full = dfixed_div(wm0->sclk, a); sclk 1210 drivers/gpu/drm/radeon/rv515.c fill_rate.full = dfixed_div(wm1->sclk, a); sclk 439 drivers/gpu/drm/radeon/rv6xx_dpm.c state->low.sclk; sclk 441 drivers/gpu/drm/radeon/rv6xx_dpm.c state->medium.sclk; sclk 443 drivers/gpu/drm/radeon/rv6xx_dpm.c state->high.sclk; sclk 1027 drivers/gpu/drm/radeon/rv6xx_dpm.c rv6xx_calculate_t(state->low.sclk, sclk 1028 drivers/gpu/drm/radeon/rv6xx_dpm.c state->medium.sclk, sclk 1035 drivers/gpu/drm/radeon/rv6xx_dpm.c rv6xx_calculate_t(state->medium.sclk, sclk 1036 drivers/gpu/drm/radeon/rv6xx_dpm.c state->high.sclk, sclk 1426 drivers/gpu/drm/radeon/rv6xx_dpm.c old_state->low.sclk, sclk 1427 drivers/gpu/drm/radeon/rv6xx_dpm.c new_state->low.sclk, sclk 1439 drivers/gpu/drm/radeon/rv6xx_dpm.c new_state->low.sclk, sclk 1460 drivers/gpu/drm/radeon/rv6xx_dpm.c new_state->low.sclk, sclk 1461 drivers/gpu/drm/radeon/rv6xx_dpm.c new_state->medium.sclk, sclk 1465 drivers/gpu/drm/radeon/rv6xx_dpm.c new_state->medium.sclk, sclk 1466 drivers/gpu/drm/radeon/rv6xx_dpm.c new_state->high.sclk, sclk 1522 drivers/gpu/drm/radeon/rv6xx_dpm.c if (new_state->high.sclk >= current_state->high.sclk) sclk 1539 drivers/gpu/drm/radeon/rv6xx_dpm.c if (new_state->high.sclk < current_state->high.sclk) sclk 1821 drivers/gpu/drm/radeon/rv6xx_dpm.c u32 sclk, mclk; sclk 1838 drivers/gpu/drm/radeon/rv6xx_dpm.c sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); sclk 1839 drivers/gpu/drm/radeon/rv6xx_dpm.c sclk |= clock_info->r600.ucEngineClockHigh << 16; sclk 1844 drivers/gpu/drm/radeon/rv6xx_dpm.c pl->sclk = sclk; sclk 1867 drivers/gpu/drm/radeon/rv6xx_dpm.c pl->sclk = rdev->clock.default_sclk; sclk 2018 drivers/gpu/drm/radeon/rv6xx_dpm.c pl->sclk, pl->mclk, pl->vddc); sclk 2021 drivers/gpu/drm/radeon/rv6xx_dpm.c pl->sclk, pl->mclk, pl->vddc); sclk 2024 drivers/gpu/drm/radeon/rv6xx_dpm.c pl->sclk, pl->mclk, pl->vddc); sclk 2049 drivers/gpu/drm/radeon/rv6xx_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc); sclk 2072 drivers/gpu/drm/radeon/rv6xx_dpm.c return pl->sclk; sclk 2115 drivers/gpu/drm/radeon/rv6xx_dpm.c return requested_state->low.sclk; sclk 2117 drivers/gpu/drm/radeon/rv6xx_dpm.c return requested_state->high.sclk; sclk 80 drivers/gpu/drm/radeon/rv6xx_dpm.h u32 sclk; sclk 41 drivers/gpu/drm/radeon/rv730_dpm.c RV770_SMC_SCLK_VALUE *sclk) sclk 108 drivers/gpu/drm/radeon/rv730_dpm.c sclk->sclk_value = cpu_to_be32(engine_clock); sclk 109 drivers/gpu/drm/radeon/rv730_dpm.c sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 110 drivers/gpu/drm/radeon/rv730_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 111 drivers/gpu/drm/radeon/rv730_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 112 drivers/gpu/drm/radeon/rv730_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); sclk 113 drivers/gpu/drm/radeon/rv730_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); sclk 304 drivers/gpu/drm/radeon/rv730_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 305 drivers/gpu/drm/radeon/rv730_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 306 drivers/gpu/drm/radeon/rv730_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 308 drivers/gpu/drm/radeon/rv730_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 344 drivers/gpu/drm/radeon/rv730_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 346 drivers/gpu/drm/radeon/rv730_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 348 drivers/gpu/drm/radeon/rv730_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 350 drivers/gpu/drm/radeon/rv730_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = sclk 352 drivers/gpu/drm/radeon/rv730_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = sclk 355 drivers/gpu/drm/radeon/rv730_dpm.c table->initialState.levels[0].sclk.sclk_value = sclk 356 drivers/gpu/drm/radeon/rv730_dpm.c cpu_to_be32(initial_state->low.sclk); sclk 405 drivers/gpu/drm/radeon/rv730_dpm.c (POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) | sclk 406 drivers/gpu/drm/radeon/rv730_dpm.c POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) | sclk 407 drivers/gpu/drm/radeon/rv730_dpm.c POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk))); sclk 415 drivers/gpu/drm/radeon/rv730_dpm.c state->high.sclk, sclk 425 drivers/gpu/drm/radeon/rv730_dpm.c state->medium.sclk, sclk 435 drivers/gpu/drm/radeon/rv730_dpm.c state->low.sclk, sclk 121 drivers/gpu/drm/radeon/rv740_dpm.c RV770_SMC_SCLK_VALUE *sclk) sclk 176 drivers/gpu/drm/radeon/rv740_dpm.c sclk->sclk_value = cpu_to_be32(engine_clock); sclk 177 drivers/gpu/drm/radeon/rv740_dpm.c sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 178 drivers/gpu/drm/radeon/rv740_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 179 drivers/gpu/drm/radeon/rv740_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 180 drivers/gpu/drm/radeon/rv740_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); sclk 181 drivers/gpu/drm/radeon/rv740_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); sclk 382 drivers/gpu/drm/radeon/rv740_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 383 drivers/gpu/drm/radeon/rv740_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 384 drivers/gpu/drm/radeon/rv740_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 386 drivers/gpu/drm/radeon/rv740_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 271 drivers/gpu/drm/radeon/rv770_dpm.c a_n = (int)state->medium.sclk * pi->lmp + sclk 272 drivers/gpu/drm/radeon/rv770_dpm.c (int)state->low.sclk * (R600_AH_DFLT - pi->rlp); sclk 273 drivers/gpu/drm/radeon/rv770_dpm.c a_d = (int)state->low.sclk * (100 - (int)pi->rlp) + sclk 274 drivers/gpu/drm/radeon/rv770_dpm.c (int)state->medium.sclk * pi->lmp; sclk 279 drivers/gpu/drm/radeon/rv770_dpm.c a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk * sclk 281 drivers/gpu/drm/radeon/rv770_dpm.c a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) + sclk 282 drivers/gpu/drm/radeon/rv770_dpm.c (int)state->high.sclk * pi->lhp; sclk 485 drivers/gpu/drm/radeon/rv770_dpm.c RV770_SMC_SCLK_VALUE *sclk) sclk 555 drivers/gpu/drm/radeon/rv770_dpm.c sclk->sclk_value = cpu_to_be32(engine_clock); sclk 556 drivers/gpu/drm/radeon/rv770_dpm.c sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 557 drivers/gpu/drm/radeon/rv770_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 558 drivers/gpu/drm/radeon/rv770_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 559 drivers/gpu/drm/radeon/rv770_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); sclk 560 drivers/gpu/drm/radeon/rv770_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); sclk 628 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv740_populate_sclk_value(rdev, pl->sclk, sclk 629 drivers/gpu/drm/radeon/rv770_dpm.c &level->sclk); sclk 631 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv730_populate_sclk_value(rdev, pl->sclk, sclk 632 drivers/gpu/drm/radeon/rv770_dpm.c &level->sclk); sclk 634 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv770_populate_sclk_value(rdev, pl->sclk, sclk 635 drivers/gpu/drm/radeon/rv770_dpm.c &level->sclk); sclk 652 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv740_populate_mclk_value(rdev, pl->sclk, sclk 655 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv730_populate_mclk_value(rdev, pl->sclk, sclk 658 drivers/gpu/drm/radeon/rv770_dpm.c ret = rv770_populate_mclk_value(rdev, pl->sclk, sclk 747 drivers/gpu/drm/radeon/rv770_dpm.c if (state->high.sclk < (state->low.sclk * 0xFF / 0x40)) sclk 748 drivers/gpu/drm/radeon/rv770_dpm.c high_clock = state->high.sclk; sclk 750 drivers/gpu/drm/radeon/rv770_dpm.c high_clock = (state->low.sclk * 0xFF / 0x40); sclk 757 drivers/gpu/drm/radeon/rv770_dpm.c STATE1(64 * high_clock / state->low.sclk) | sclk 758 drivers/gpu/drm/radeon/rv770_dpm.c STATE2(64 * high_clock / state->medium.sclk) | sclk 759 drivers/gpu/drm/radeon/rv770_dpm.c STATE3(64 * high_clock / state->high.sclk); sclk 764 drivers/gpu/drm/radeon/rv770_dpm.c POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) | sclk 765 drivers/gpu/drm/radeon/rv770_dpm.c POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) | sclk 766 drivers/gpu/drm/radeon/rv770_dpm.c POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk)); sclk 991 drivers/gpu/drm/radeon/rv770_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); sclk 992 drivers/gpu/drm/radeon/rv770_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); sclk 993 drivers/gpu/drm/radeon/rv770_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); sclk 995 drivers/gpu/drm/radeon/rv770_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 1051 drivers/gpu/drm/radeon/rv770_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 1053 drivers/gpu/drm/radeon/rv770_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 1055 drivers/gpu/drm/radeon/rv770_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 1057 drivers/gpu/drm/radeon/rv770_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = sclk 1059 drivers/gpu/drm/radeon/rv770_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = sclk 1062 drivers/gpu/drm/radeon/rv770_dpm.c table->initialState.levels[0].sclk.sclk_value = sclk 1063 drivers/gpu/drm/radeon/rv770_dpm.c cpu_to_be32(initial_state->low.sclk); sclk 1171 drivers/gpu/drm/radeon/rv770_dpm.c pi->boot_sclk = boot_state->low.sclk; sclk 1442 drivers/gpu/drm/radeon/rv770_dpm.c if (new_state->high.sclk >= current_state->high.sclk) sclk 1459 drivers/gpu/drm/radeon/rv770_dpm.c if (new_state->high.sclk < current_state->high.sclk) sclk 2180 drivers/gpu/drm/radeon/rv770_dpm.c u32 sclk, mclk; sclk 2197 drivers/gpu/drm/radeon/rv770_dpm.c sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); sclk 2198 drivers/gpu/drm/radeon/rv770_dpm.c sclk |= clock_info->evergreen.ucEngineClockHigh << 16; sclk 2206 drivers/gpu/drm/radeon/rv770_dpm.c sclk = le16_to_cpu(clock_info->r600.usEngineClockLow); sclk 2207 drivers/gpu/drm/radeon/rv770_dpm.c sclk |= clock_info->r600.ucEngineClockHigh << 16; sclk 2216 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk = sclk; sclk 2252 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk = rdev->clock.default_sclk; sclk 2259 drivers/gpu/drm/radeon/rv770_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; sclk 2444 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 2447 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 2450 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 2454 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk, pl->mclk, pl->vddc); sclk 2457 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk, pl->mclk, pl->vddc); sclk 2460 drivers/gpu/drm/radeon/rv770_dpm.c pl->sclk, pl->mclk, pl->vddc); sclk 2487 drivers/gpu/drm/radeon/rv770_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci); sclk 2490 drivers/gpu/drm/radeon/rv770_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc); sclk 2513 drivers/gpu/drm/radeon/rv770_dpm.c return pl->sclk; sclk 2555 drivers/gpu/drm/radeon/rv770_dpm.c return requested_state->low.sclk; sclk 2557 drivers/gpu/drm/radeon/rv770_dpm.c return requested_state->high.sclk; sclk 143 drivers/gpu/drm/radeon/rv770_dpm.h u32 sclk; sclk 182 drivers/gpu/drm/radeon/rv770_dpm.h RV770_SMC_SCLK_VALUE *sclk); sclk 203 drivers/gpu/drm/radeon/rv770_dpm.h RV770_SMC_SCLK_VALUE *sclk); sclk 108 drivers/gpu/drm/radeon/rv770_smc.h RV770_SMC_SCLK_VALUE sclk; sclk 2060 drivers/gpu/drm/radeon/si.c u32 sclk; /* engine clock in kHz */ sclk 2117 drivers/gpu/drm/radeon/si.c fixed20_12 sclk, bandwidth; sclk 2121 drivers/gpu/drm/radeon/si.c sclk.full = dfixed_const(wm->sclk); sclk 2122 drivers/gpu/drm/radeon/si.c sclk.full = dfixed_div(sclk, a); sclk 2127 drivers/gpu/drm/radeon/si.c bandwidth.full = dfixed_mul(a, sclk); sclk 2142 drivers/gpu/drm/radeon/si.c fixed20_12 disp_clk, sclk, bandwidth; sclk 2153 drivers/gpu/drm/radeon/si.c sclk.full = dfixed_const(wm->sclk); sclk 2154 drivers/gpu/drm/radeon/si.c sclk.full = dfixed_div(sclk, a); sclk 2156 drivers/gpu/drm/radeon/si.c b2.full = dfixed_mul(a, sclk); sclk 2332 drivers/gpu/drm/radeon/si.c wm_high.sclk = sclk 2336 drivers/gpu/drm/radeon/si.c wm_high.sclk = rdev->pm.current_sclk * 10; sclk 2359 drivers/gpu/drm/radeon/si.c wm_low.sclk = sclk 2363 drivers/gpu/drm/radeon/si.c wm_low.sclk = rdev->pm.current_sclk * 10; sclk 1760 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SCLK_VALUE *sclk); sclk 2325 drivers/gpu/drm/radeon/si_dpm.c prev_sclk = state->performance_levels[i-1].sclk; sclk 2326 drivers/gpu/drm/radeon/si_dpm.c max_sclk = state->performance_levels[i].sclk; sclk 2345 drivers/gpu/drm/radeon/si_dpm.c if (min_sclk < state->performance_levels[0].sclk) sclk 2346 drivers/gpu/drm/radeon/si_dpm.c min_sclk = state->performance_levels[0].sclk; sclk 2420 drivers/gpu/drm/radeon/si_dpm.c if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && sclk 2855 drivers/gpu/drm/radeon/si_dpm.c u32 sclk = 0; sclk 2868 drivers/gpu/drm/radeon/si_dpm.c ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); sclk 2901 drivers/gpu/drm/radeon/si_dpm.c sclk += 512; sclk 2975 drivers/gpu/drm/radeon/si_dpm.c u32 mclk, sclk; sclk 3039 drivers/gpu/drm/radeon/si_dpm.c if (ps->performance_levels[i].sclk > max_limits->sclk) sclk 3040 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[i].sclk = max_limits->sclk; sclk 3058 drivers/gpu/drm/radeon/si_dpm.c if (ps->performance_levels[i].sclk > max_sclk_vddc) sclk 3059 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[i].sclk = max_sclk_vddc; sclk 3074 drivers/gpu/drm/radeon/si_dpm.c if (ps->performance_levels[i].sclk > max_sclk) sclk 3075 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[i].sclk = max_sclk; sclk 3090 drivers/gpu/drm/radeon/si_dpm.c sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; sclk 3093 drivers/gpu/drm/radeon/si_dpm.c sclk = ps->performance_levels[0].sclk; sclk 3098 drivers/gpu/drm/radeon/si_dpm.c if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) sclk 3099 drivers/gpu/drm/radeon/si_dpm.c sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; sclk 3105 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[0].sclk = sclk; sclk 3111 drivers/gpu/drm/radeon/si_dpm.c sclk = ps->performance_levels[0].sclk; sclk 3113 drivers/gpu/drm/radeon/si_dpm.c if (sclk < ps->performance_levels[i].sclk) sclk 3114 drivers/gpu/drm/radeon/si_dpm.c sclk = ps->performance_levels[i].sclk; sclk 3117 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[i].sclk = sclk; sclk 3122 drivers/gpu/drm/radeon/si_dpm.c if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) sclk 3123 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; sclk 3156 drivers/gpu/drm/radeon/si_dpm.c ps->performance_levels[i].sclk, sclk 4211 drivers/gpu/drm/radeon/si_dpm.c u16 voltage, u32 sclk, u32 mclk, sclk 4218 drivers/gpu/drm/radeon/si_dpm.c (sclk <= limits->entries[i].sclk) && sclk 4302 drivers/gpu/drm/radeon/si_dpm.c (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); sclk 4305 drivers/gpu/drm/radeon/si_dpm.c pl->sclk, sclk 4399 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 4401 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 4403 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 4405 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = sclk 4407 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = sclk 4409 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = sclk 4412 drivers/gpu/drm/radeon/si_dpm.c table->initialState.levels[0].sclk.sclk_value = sclk 4413 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(initial_state->performance_levels[0].sclk); sclk 4446 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].sclk, sclk 4598 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = sclk 4600 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = sclk 4602 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = sclk 4604 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = sclk 4608 drivers/gpu/drm/radeon/si_dpm.c table->ACPIState.levels[0].sclk.sclk_value = 0; sclk 4784 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SCLK_VALUE *sclk) sclk 4841 drivers/gpu/drm/radeon/si_dpm.c sclk->sclk_value = engine_clock; sclk 4842 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; sclk 4843 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; sclk 4844 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; sclk 4845 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; sclk 4846 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; sclk 4847 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; sclk 4854 drivers/gpu/drm/radeon/si_dpm.c SISLANDS_SMC_SCLK_VALUE *sclk) sclk 4861 drivers/gpu/drm/radeon/si_dpm.c sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); sclk 4862 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); sclk 4863 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); sclk 4864 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); sclk 4865 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); sclk 4866 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); sclk 4867 drivers/gpu/drm/radeon/si_dpm.c sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); sclk 4995 drivers/gpu/drm/radeon/si_dpm.c ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); sclk 5038 drivers/gpu/drm/radeon/si_dpm.c pl->sclk, sclk 5072 drivers/gpu/drm/radeon/si_dpm.c pl->sclk, sclk 5112 drivers/gpu/drm/radeon/si_dpm.c state->performance_levels[i + 1].sclk, sclk 5113 drivers/gpu/drm/radeon/si_dpm.c state->performance_levels[i].sclk, sclk 5204 drivers/gpu/drm/radeon/si_dpm.c threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; sclk 5238 drivers/gpu/drm/radeon/si_dpm.c (state->performance_levels[i].sclk < threshold) ? sclk 6746 drivers/gpu/drm/radeon/si_dpm.c pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); sclk 6747 drivers/gpu/drm/radeon/si_dpm.c pl->sclk |= clock_info->si.ucEngineClockHigh << 16; sclk 6793 drivers/gpu/drm/radeon/si_dpm.c pl->sclk = rdev->clock.default_sclk; sclk 6801 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; sclk 6885 drivers/gpu/drm/radeon/si_dpm.c u32 sclk, mclk; sclk 6889 drivers/gpu/drm/radeon/si_dpm.c sclk = le16_to_cpu(clock_info->si.usEngineClockLow); sclk 6890 drivers/gpu/drm/radeon/si_dpm.c sclk |= clock_info->si.ucEngineClockHigh << 16; sclk 6893 drivers/gpu/drm/radeon/si_dpm.c rdev->pm.dpm.vce_states[i].sclk = sclk; sclk 7069 drivers/gpu/drm/radeon/si_dpm.c if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || sclk 7109 drivers/gpu/drm/radeon/si_dpm.c current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); sclk 7127 drivers/gpu/drm/radeon/si_dpm.c return pl->sclk; sclk 153 drivers/gpu/drm/radeon/sislands_smc.h SISLANDS_SMC_SCLK_VALUE sclk; sclk 347 drivers/gpu/drm/radeon/sumo_dpm.c u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; sclk 350 drivers/gpu/drm/radeon/sumo_dpm.c highest_engine_clock = pi->boost_pl.sclk; sclk 411 drivers/gpu/drm/radeon/sumo_dpm.c m_a = asi * ps->levels[i].sclk / 100; sclk 421 drivers/gpu/drm/radeon/sumo_dpm.c m_a = asi * pi->boost_pl.sclk / 100; sclk 555 drivers/gpu/drm/radeon/sumo_dpm.c pl->sclk, false, ÷rs); sclk 671 drivers/gpu/drm/radeon/sumo_dpm.c pi->boost_pl.sclk = pi->sys_info.boost_sclk; sclk 790 drivers/gpu/drm/radeon/sumo_dpm.c pi->acpi_pl.sclk, sclk 844 drivers/gpu/drm/radeon/sumo_dpm.c if (new_ps->levels[new_ps->num_levels - 1].sclk >= sclk 845 drivers/gpu/drm/radeon/sumo_dpm.c current_ps->levels[current_ps->num_levels - 1].sclk) sclk 862 drivers/gpu/drm/radeon/sumo_dpm.c if (new_ps->levels[new_ps->num_levels - 1].sclk < sclk 863 drivers/gpu/drm/radeon/sumo_dpm.c current_ps->levels[current_ps->num_levels - 1].sclk) sclk 1004 drivers/gpu/drm/radeon/sumo_dpm.c u32 sclk, sclk 1013 drivers/gpu/drm/radeon/sumo_dpm.c if (sclk < min) sclk 1020 drivers/gpu/drm/radeon/sumo_dpm.c temp = sclk / sumo_get_sleep_divider_from_id(i); sclk 1054 drivers/gpu/drm/radeon/sumo_dpm.c current_sclk = current_ps->levels[current_index].sclk; sclk 1057 drivers/gpu/drm/radeon/sumo_dpm.c current_sclk = pi->boot_pl.sclk; sclk 1062 drivers/gpu/drm/radeon/sumo_dpm.c if (ps->levels[0].sclk > current_sclk) sclk 1063 drivers/gpu/drm/radeon/sumo_dpm.c ps->levels[0].sclk = current_sclk; sclk 1066 drivers/gpu/drm/radeon/sumo_dpm.c sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); sclk 1069 drivers/gpu/drm/radeon/sumo_dpm.c sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK); sclk 1115 drivers/gpu/drm/radeon/sumo_dpm.c if (ps->levels[i].sclk < min_sclk) sclk 1116 drivers/gpu/drm/radeon/sumo_dpm.c ps->levels[i].sclk = sclk 1120 drivers/gpu/drm/radeon/sumo_dpm.c sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); sclk 1123 drivers/gpu/drm/radeon/sumo_dpm.c sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK); sclk 1436 drivers/gpu/drm/radeon/sumo_dpm.c u32 sclk; sclk 1438 drivers/gpu/drm/radeon/sumo_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 1439 drivers/gpu/drm/radeon/sumo_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 1440 drivers/gpu/drm/radeon/sumo_dpm.c pl->sclk = sclk; sclk 1730 drivers/gpu/drm/radeon/sumo_dpm.c pi->boot_pl.sclk = pi->sys_info.bootup_sclk; sclk 1806 drivers/gpu/drm/radeon/sumo_dpm.c i, pl->sclk, sclk 1827 drivers/gpu/drm/radeon/sumo_dpm.c current_index, pl->sclk, sclk 1835 drivers/gpu/drm/radeon/sumo_dpm.c current_index, pl->sclk, sclk 1852 drivers/gpu/drm/radeon/sumo_dpm.c return pl->sclk; sclk 1857 drivers/gpu/drm/radeon/sumo_dpm.c return pl->sclk; sclk 1887 drivers/gpu/drm/radeon/sumo_dpm.c return requested_state->levels[0].sclk; sclk 1889 drivers/gpu/drm/radeon/sumo_dpm.c return requested_state->levels[requested_state->num_levels - 1].sclk; sclk 33 drivers/gpu/drm/radeon/sumo_dpm.h u32 sclk; sclk 208 drivers/gpu/drm/radeon/sumo_dpm.h u32 sclk, sclk 585 drivers/gpu/drm/radeon/trinity_dpm.c u32 index, u32 sclk) sclk 593 drivers/gpu/drm/radeon/trinity_dpm.c sclk, false, ÷rs); sclk 603 drivers/gpu/drm/radeon/trinity_dpm.c sclk/2, false, ÷rs); sclk 723 drivers/gpu/drm/radeon/trinity_dpm.c trinity_set_divider_value(rdev, index, pl->sclk); sclk 970 drivers/gpu/drm/radeon/trinity_dpm.c if (new_ps->levels[new_ps->num_levels - 1].sclk >= sclk 971 drivers/gpu/drm/radeon/trinity_dpm.c current_ps->levels[current_ps->num_levels - 1].sclk) sclk 984 drivers/gpu/drm/radeon/trinity_dpm.c if (new_ps->levels[new_ps->num_levels - 1].sclk < sclk 985 drivers/gpu/drm/radeon/trinity_dpm.c current_ps->levels[current_ps->num_levels - 1].sclk) sclk 1335 drivers/gpu/drm/radeon/trinity_dpm.c static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) sclk 1337 drivers/gpu/drm/radeon/trinity_dpm.c if (sclk < 20000) sclk 1346 drivers/gpu/drm/radeon/trinity_dpm.c pi->boot_pl.sclk = pi->sys_info.bootup_sclk; sclk 1359 drivers/gpu/drm/radeon/trinity_dpm.c u32 sclk, u32 min_sclk_in_sr) sclk 1367 drivers/gpu/drm/radeon/trinity_dpm.c if (sclk < min) sclk 1374 drivers/gpu/drm/radeon/trinity_dpm.c temp = sclk / sumo_get_sleep_divider_from_id(i); sclk 1411 drivers/gpu/drm/radeon/trinity_dpm.c current_sclk = current_ps->levels[current_index].sclk; sclk 1414 drivers/gpu/drm/radeon/trinity_dpm.c current_sclk = pi->boot_pl.sclk; sclk 1419 drivers/gpu/drm/radeon/trinity_dpm.c if (ps->levels[0].sclk > current_sclk) sclk 1420 drivers/gpu/drm/radeon/trinity_dpm.c ps->levels[0].sclk = current_sclk; sclk 1423 drivers/gpu/drm/radeon/trinity_dpm.c trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); sclk 1429 drivers/gpu/drm/radeon/trinity_dpm.c trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); sclk 1445 drivers/gpu/drm/radeon/trinity_dpm.c else if (ps->levels[index].sclk < 30000) sclk 1567 drivers/gpu/drm/radeon/trinity_dpm.c if (ps->levels[i].sclk < min_sclk) sclk 1568 drivers/gpu/drm/radeon/trinity_dpm.c ps->levels[i].sclk = sclk 1574 drivers/gpu/drm/radeon/trinity_dpm.c if (ps->levels[i].sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) sclk 1575 drivers/gpu/drm/radeon/trinity_dpm.c ps->levels[i].sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; sclk 1583 drivers/gpu/drm/radeon/trinity_dpm.c sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); sclk 1592 drivers/gpu/drm/radeon/trinity_dpm.c trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); sclk 1715 drivers/gpu/drm/radeon/trinity_dpm.c u32 sclk; sclk 1717 drivers/gpu/drm/radeon/trinity_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 1718 drivers/gpu/drm/radeon/trinity_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 1719 drivers/gpu/drm/radeon/trinity_dpm.c pl->sclk = sclk; sclk 1807 drivers/gpu/drm/radeon/trinity_dpm.c u32 sclk; sclk 1811 drivers/gpu/drm/radeon/trinity_dpm.c sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); sclk 1812 drivers/gpu/drm/radeon/trinity_dpm.c sclk |= clock_info->sumo.ucEngineClockHigh << 16; sclk 1813 drivers/gpu/drm/radeon/trinity_dpm.c rdev->pm.dpm.vce_states[i].sclk = sclk; sclk 2024 drivers/gpu/drm/radeon/trinity_dpm.c i, pl->sclk, sclk 2047 drivers/gpu/drm/radeon/trinity_dpm.c current_index, pl->sclk, sclk 2066 drivers/gpu/drm/radeon/trinity_dpm.c return pl->sclk; sclk 2097 drivers/gpu/drm/radeon/trinity_dpm.c return requested_state->levels[0].sclk; sclk 2099 drivers/gpu/drm/radeon/trinity_dpm.c return requested_state->levels[requested_state->num_levels - 1].sclk; sclk 31 drivers/gpu/drm/radeon/trinity_dpm.h u32 sclk; sclk 70 drivers/i2c/busses/i2c-emev2.c struct clk *sclk; sclk 378 drivers/i2c/busses/i2c-emev2.c priv->sclk = devm_clk_get(&pdev->dev, "sclk"); sclk 379 drivers/i2c/busses/i2c-emev2.c if (IS_ERR(priv->sclk)) sclk 380 drivers/i2c/busses/i2c-emev2.c return PTR_ERR(priv->sclk); sclk 382 drivers/i2c/busses/i2c-emev2.c ret = clk_prepare_enable(priv->sclk); sclk 417 drivers/i2c/busses/i2c-emev2.c clk_disable_unprepare(priv->sclk); sclk 426 drivers/i2c/busses/i2c-emev2.c clk_disable_unprepare(priv->sclk); sclk 127 drivers/iio/adc/exynos_adc.c struct clk *sclk; sclk 159 drivers/iio/adc/exynos_adc.c clk_unprepare(info->sclk); sclk 174 drivers/iio/adc/exynos_adc.c ret = clk_prepare(info->sclk); sclk 189 drivers/iio/adc/exynos_adc.c clk_disable(info->sclk); sclk 204 drivers/iio/adc/exynos_adc.c ret = clk_enable(info->sclk); sclk 830 drivers/iio/adc/exynos_adc.c info->sclk = devm_clk_get(&pdev->dev, "sclk"); sclk 831 drivers/iio/adc/exynos_adc.c if (IS_ERR(info->sclk)) { sclk 834 drivers/iio/adc/exynos_adc.c PTR_ERR(info->sclk)); sclk 835 drivers/iio/adc/exynos_adc.c return PTR_ERR(info->sclk); sclk 544 drivers/media/dvb-frontends/cx24110.c s32 afc; unsigned sclk; sclk 548 drivers/media/dvb-frontends/cx24110.c sclk = cx24110_readreg (state, 0x07) & 0x03; sclk 551 drivers/media/dvb-frontends/cx24110.c if (sclk==0) sclk=90999000L/2L; sclk 552 drivers/media/dvb-frontends/cx24110.c else if (sclk==1) sclk=60666000L; sclk 553 drivers/media/dvb-frontends/cx24110.c else if (sclk==2) sclk=80888000L; sclk 554 drivers/media/dvb-frontends/cx24110.c else sclk=90999000L; sclk 555 drivers/media/dvb-frontends/cx24110.c sclk>>=8; sclk 556 drivers/media/dvb-frontends/cx24110.c afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ sclk 557 drivers/media/dvb-frontends/cx24110.c ((sclk*cx24110_readreg (state, 0x45))>>8)+ sclk 558 drivers/media/dvb-frontends/cx24110.c ((sclk*cx24110_readreg (state, 0x46))>>16); sclk 709 drivers/media/platform/rockchip/rga/rga.c ret = clk_prepare_enable(rga->sclk); sclk 730 drivers/media/platform/rockchip/rga/rga.c clk_disable_unprepare(rga->sclk); sclk 739 drivers/media/platform/rockchip/rga/rga.c clk_disable_unprepare(rga->sclk); sclk 778 drivers/media/platform/rockchip/rga/rga.c rga->sclk = devm_clk_get(rga->dev, "sclk"); sclk 779 drivers/media/platform/rockchip/rga/rga.c if (IS_ERR(rga->sclk)) { sclk 781 drivers/media/platform/rockchip/rga/rga.c return PTR_ERR(rga->sclk); sclk 71 drivers/media/platform/rockchip/rga/rga.h struct clk *sclk; sclk 754 drivers/mmc/host/mtk-sd.c u32 sclk; sclk 782 drivers/mmc/host/mtk-sd.c sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ sclk 785 drivers/mmc/host/mtk-sd.c sclk = (host->src_clk_freq >> 2) / div; sclk 797 drivers/mmc/host/mtk-sd.c sclk = host->src_clk_freq >> 1; sclk 803 drivers/mmc/host/mtk-sd.c sclk = host->src_clk_freq; sclk 808 drivers/mmc/host/mtk-sd.c sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ sclk 811 drivers/mmc/host/mtk-sd.c sclk = (host->src_clk_freq >> 2) / div; sclk 839 drivers/mmc/host/mtk-sd.c host->mmc->actual_clock = sclk; sclk 67 drivers/mtd/spi-nor/cadence-quadspi.c unsigned int sclk; sclk 787 drivers/mtd/spi-nor/cadence-quadspi.c tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); sclk 816 drivers/mtd/spi-nor/cadence-quadspi.c div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; sclk 866 drivers/mtd/spi-nor/cadence-quadspi.c const unsigned int sclk = f_pdata->clk_rate; sclk 868 drivers/mtd/spi-nor/cadence-quadspi.c int switch_ck = (cqspi->sclk != sclk); sclk 886 drivers/mtd/spi-nor/cadence-quadspi.c cqspi->sclk = sclk; sclk 1422 drivers/mtd/spi-nor/cadence-quadspi.c cqspi->sclk = 0; sclk 55 drivers/power/reset/at91-poweroff.c struct clk *sclk; sclk 164 drivers/power/reset/at91-poweroff.c at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL); sclk 165 drivers/power/reset/at91-poweroff.c if (IS_ERR(at91_shdwc.sclk)) sclk 166 drivers/power/reset/at91-poweroff.c return PTR_ERR(at91_shdwc.sclk); sclk 168 drivers/power/reset/at91-poweroff.c ret = clk_prepare_enable(at91_shdwc.sclk); sclk 203 drivers/power/reset/at91-poweroff.c clk_disable_unprepare(at91_shdwc.sclk); sclk 215 drivers/power/reset/at91-poweroff.c clk_disable_unprepare(at91_shdwc.sclk); sclk 53 drivers/power/reset/at91-reset.c static struct clk *sclk; sclk 235 drivers/power/reset/at91-reset.c sclk = devm_clk_get(&pdev->dev, NULL); sclk 236 drivers/power/reset/at91-reset.c if (IS_ERR(sclk)) sclk 237 drivers/power/reset/at91-reset.c return PTR_ERR(sclk); sclk 239 drivers/power/reset/at91-reset.c ret = clk_prepare_enable(sclk); sclk 247 drivers/power/reset/at91-reset.c clk_disable_unprepare(sclk); sclk 259 drivers/power/reset/at91-reset.c clk_disable_unprepare(sclk); sclk 79 drivers/power/reset/at91-sama5d2_shdwc.c struct clk *sclk; sclk 302 drivers/power/reset/at91-sama5d2_shdwc.c at91_shdwc->sclk = devm_clk_get(&pdev->dev, NULL); sclk 303 drivers/power/reset/at91-sama5d2_shdwc.c if (IS_ERR(at91_shdwc->sclk)) sclk 304 drivers/power/reset/at91-sama5d2_shdwc.c return PTR_ERR(at91_shdwc->sclk); sclk 306 drivers/power/reset/at91-sama5d2_shdwc.c ret = clk_prepare_enable(at91_shdwc->sclk); sclk 359 drivers/power/reset/at91-sama5d2_shdwc.c clk_disable_unprepare(at91_shdwc->sclk); sclk 379 drivers/power/reset/at91-sama5d2_shdwc.c clk_disable_unprepare(shdw->sclk); sclk 55 drivers/rtc/rtc-at91rm9200.c static struct clk *sclk; sclk 396 drivers/rtc/rtc-at91rm9200.c sclk = devm_clk_get(&pdev->dev, NULL); sclk 397 drivers/rtc/rtc-at91rm9200.c if (IS_ERR(sclk)) sclk 398 drivers/rtc/rtc-at91rm9200.c return PTR_ERR(sclk); sclk 400 drivers/rtc/rtc-at91rm9200.c ret = clk_prepare_enable(sclk); sclk 444 drivers/rtc/rtc-at91rm9200.c clk_disable_unprepare(sclk); sclk 459 drivers/rtc/rtc-at91rm9200.c clk_disable_unprepare(sclk); sclk 75 drivers/rtc/rtc-at91sam9.c struct clk *sclk; sclk 379 drivers/rtc/rtc-at91sam9.c rtc->sclk = devm_clk_get(&pdev->dev, NULL); sclk 380 drivers/rtc/rtc-at91sam9.c if (IS_ERR(rtc->sclk)) sclk 381 drivers/rtc/rtc-at91sam9.c return PTR_ERR(rtc->sclk); sclk 383 drivers/rtc/rtc-at91sam9.c ret = clk_prepare_enable(rtc->sclk); sclk 389 drivers/rtc/rtc-at91sam9.c sclk_rate = clk_get_rate(rtc->sclk); sclk 439 drivers/rtc/rtc-at91sam9.c clk_disable_unprepare(rtc->sclk); sclk 455 drivers/rtc/rtc-at91sam9.c clk_disable_unprepare(rtc->sclk); sclk 181 drivers/thermal/samsung/exynos_tmu.c struct clk *clk, *clk_sec, *sclk; sclk 1070 drivers/thermal/samsung/exynos_tmu.c data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); sclk 1071 drivers/thermal/samsung/exynos_tmu.c if (IS_ERR(data->sclk)) { sclk 1075 drivers/thermal/samsung/exynos_tmu.c ret = clk_prepare_enable(data->sclk); sclk 1117 drivers/thermal/samsung/exynos_tmu.c clk_disable_unprepare(data->sclk); sclk 1138 drivers/thermal/samsung/exynos_tmu.c clk_disable_unprepare(data->sclk); sclk 24 drivers/tty/serial/8250/8250_em.c struct clk *sclk; sclk 96 drivers/tty/serial/8250/8250_em.c priv->sclk = devm_clk_get(&pdev->dev, "sclk"); sclk 97 drivers/tty/serial/8250/8250_em.c if (IS_ERR(priv->sclk)) { sclk 99 drivers/tty/serial/8250/8250_em.c return PTR_ERR(priv->sclk); sclk 110 drivers/tty/serial/8250/8250_em.c clk_prepare_enable(priv->sclk); sclk 111 drivers/tty/serial/8250/8250_em.c up.port.uartclk = clk_get_rate(priv->sclk); sclk 122 drivers/tty/serial/8250/8250_em.c clk_disable_unprepare(priv->sclk); sclk 136 drivers/tty/serial/8250/8250_em.c clk_disable_unprepare(priv->sclk); sclk 50 drivers/video/fbdev/aty/atyfb.h int sclk, mclk, mclk_pm, xclk; sclk 3375 drivers/video/fbdev/aty/atyfb_base.c par->pll_limits.sclk = pll_block.SCLK_freq/100; sclk 565 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = (*val) / 10; sclk 582 drivers/video/fbdev/aty/radeon_base.c unsigned sclk, mclk, tmp, ref_div; sclk 697 drivers/video/fbdev/aty/radeon_base.c sclk = round_div((2 * Ns * xtal), (2 * M)); sclk 703 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = sclk; sclk 725 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 23000; sclk 736 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 27500; sclk 746 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 25000; sclk 756 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 27000; sclk 767 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 16600; sclk 791 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); sclk 824 drivers/video/fbdev/aty/radeon_base.c if (rinfo->pll.sclk == 0) sclk 825 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk = 20000; sclk 831 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); sclk 141 drivers/video/fbdev/aty/radeonfb.h int sclk, mclk; sclk 91 drivers/watchdog/at91sam9_wdt.c struct clk *sclk; sclk 352 drivers/watchdog/at91sam9_wdt.c wdt->sclk = devm_clk_get(&pdev->dev, NULL); sclk 353 drivers/watchdog/at91sam9_wdt.c if (IS_ERR(wdt->sclk)) sclk 354 drivers/watchdog/at91sam9_wdt.c return PTR_ERR(wdt->sclk); sclk 356 drivers/watchdog/at91sam9_wdt.c err = clk_prepare_enable(wdt->sclk); sclk 380 drivers/watchdog/at91sam9_wdt.c clk_disable_unprepare(wdt->sclk); sclk 392 drivers/watchdog/at91sam9_wdt.c clk_disable_unprepare(wdt->sclk); sclk 1036 include/uapi/drm/amdgpu_drm.h __u32 sclk; sclk 34 sound/aoa/soundbus/i2sbus/pcm.c static int clock_and_divisors(int mclk, int sclk, int rate, int *out) sclk 37 sound/aoa/soundbus/i2sbus/pcm.c if (mclk % sclk) sclk 40 sound/aoa/soundbus/i2sbus/pcm.c if (i2s_sf_sclkdiv(mclk / sclk, out)) sclk 548 sound/soc/bcm/cygnus-ssp.c u32 sclk; sclk 586 sound/soc/bcm/cygnus-ssp.c sclk = aio->bit_per_frame; sclk 587 sound/soc/bcm/cygnus-ssp.c if (sclk == 512) sclk 588 sound/soc/bcm/cygnus-ssp.c sclk = 0; sclk 591 sound/soc/bcm/cygnus-ssp.c sclk /= 32; sclk 596 sound/soc/bcm/cygnus-ssp.c value |= sclk << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32; sclk 75 sound/soc/cirrus/ep93xx-i2s.c struct clk *sclk; sclk 115 sound/soc/cirrus/ep93xx-i2s.c clk_enable(info->sclk); sclk 160 sound/soc/cirrus/ep93xx-i2s.c clk_disable(info->sclk); sclk 343 sound/soc/cirrus/ep93xx-i2s.c err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); sclk 347 sound/soc/cirrus/ep93xx-i2s.c err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); sclk 460 sound/soc/cirrus/ep93xx-i2s.c info->sclk = clk_get(&pdev->dev, "sclk"); sclk 461 sound/soc/cirrus/ep93xx-i2s.c if (IS_ERR(info->sclk)) { sclk 462 sound/soc/cirrus/ep93xx-i2s.c err = PTR_ERR(info->sclk); sclk 488 sound/soc/cirrus/ep93xx-i2s.c clk_put(info->sclk); sclk 500 sound/soc/cirrus/ep93xx-i2s.c clk_put(info->sclk); sclk 552 sound/soc/codecs/cs35l35.c if ((cs35l35->sclk / srate) % 4) { sclk 554 sound/soc/codecs/cs35l35.c cs35l35->sclk, srate); sclk 557 sound/soc/codecs/cs35l35.c sp_sclks = ((cs35l35->sclk / srate) / 4) - 1; sclk 658 sound/soc/codecs/cs35l35.c cs35l35->sclk = freq; sclk 282 sound/soc/codecs/cs35l35.h int sclk; sclk 576 sound/soc/codecs/cs42l42.c u32 sclk; sclk 617 sound/soc/codecs/cs42l42.c if (pll_ratio_table[i].sclk == cs42l42->sclk) { sclk 637 sound/soc/codecs/cs42l42.c fsync = cs42l42->sclk / cs42l42->srate; sclk 638 sound/soc/codecs/cs42l42.c if (((fsync * cs42l42->srate) != cs42l42->sclk) sclk 642 sound/soc/codecs/cs42l42.c cs42l42->sclk, sclk 847 sound/soc/codecs/cs42l42.c cs42l42->sclk = freq; sclk 757 sound/soc/codecs/cs42l42.h u32 sclk; sclk 836 sound/soc/codecs/cs43130.c unsigned int sclk = cs43130->dais[dai->id].sclk; sclk 867 sound/soc/codecs/cs43130.c sclk = params_rate(params) * bitwidth_dai * sclk 912 sound/soc/codecs/cs43130.c if (!sclk && cs43130->dais[dai->id].dai_mode == SND_SOC_DAIFMT_CBM_CFM) sclk 914 sound/soc/codecs/cs43130.c sclk = params_rate(params) * bitwidth_dai * sclk 917 sound/soc/codecs/cs43130.c if (!sclk) { sclk 923 sound/soc/codecs/cs43130.c bitwidth_sclk = (sclk / params_rate(params)) / params_channels(params); sclk 931 sound/soc/codecs/cs43130.c sclk, params_rate(params), bitwidth_dai); sclk 1542 sound/soc/codecs/cs43130.c cs43130->dais[codec_dai->id].sclk = freq; sclk 1544 sound/soc/codecs/cs43130.c cs43130->dais[codec_dai->id].sclk); sclk 496 sound/soc/codecs/cs43130.h unsigned int sclk; sclk 632 sound/soc/codecs/nau8810.c int i, sclk, imclk = rate * 256, div = 0; sclk 644 sound/soc/codecs/nau8810.c sclk = (nau8810->sysclk * 10) / sclk 646 sound/soc/codecs/nau8810.c if (sclk < imclk) sclk 671 sound/soc/codecs/nau8822.c int i, sclk, imclk; sclk 682 sound/soc/codecs/nau8822.c sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i]; sclk 683 sound/soc/codecs/nau8822.c if (sclk < imclk) sclk 34 sound/soc/codecs/pcm512x.c struct clk *sclk; sclk 588 sound/soc/codecs/pcm512x.c if (IS_ERR(pcm512x->sclk)) { sclk 590 sound/soc/codecs/pcm512x.c PTR_ERR(pcm512x->sclk)); sclk 591 sound/soc/codecs/pcm512x.c return PTR_ERR(pcm512x->sclk); sclk 611 sound/soc/codecs/pcm512x.c rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; sclk 629 sound/soc/codecs/pcm512x.c if (IS_ERR(pcm512x->sclk)) { sclk 631 sound/soc/codecs/pcm512x.c PTR_ERR(pcm512x->sclk)); sclk 923 sound/soc/codecs/pcm512x.c sck_rate = clk_get_rate(pcm512x->sclk); sclk 940 sound/soc/codecs/pcm512x.c pllin_rate = clk_get_rate(pcm512x->sclk); sclk 1566 sound/soc/codecs/pcm512x.c pcm512x->sclk = devm_clk_get(dev, NULL); sclk 1567 sound/soc/codecs/pcm512x.c if (PTR_ERR(pcm512x->sclk) == -EPROBE_DEFER) { sclk 1571 sound/soc/codecs/pcm512x.c if (!IS_ERR(pcm512x->sclk)) { sclk 1572 sound/soc/codecs/pcm512x.c ret = clk_prepare_enable(pcm512x->sclk); sclk 1641 sound/soc/codecs/pcm512x.c if (!IS_ERR(pcm512x->sclk)) sclk 1642 sound/soc/codecs/pcm512x.c clk_disable_unprepare(pcm512x->sclk); sclk 1655 sound/soc/codecs/pcm512x.c if (!IS_ERR(pcm512x->sclk)) sclk 1656 sound/soc/codecs/pcm512x.c clk_disable_unprepare(pcm512x->sclk); sclk 1682 sound/soc/codecs/pcm512x.c if (!IS_ERR(pcm512x->sclk)) sclk 1683 sound/soc/codecs/pcm512x.c clk_disable_unprepare(pcm512x->sclk); sclk 1693 sound/soc/codecs/pcm512x.c if (!IS_ERR(pcm512x->sclk)) { sclk 1694 sound/soc/codecs/pcm512x.c ret = clk_prepare_enable(pcm512x->sclk); sclk 37 sound/soc/codecs/rk3328_codec.c unsigned int sclk; sclk 222 sound/soc/codecs/rl6231.c int rl6231_get_clk_info(int sclk, int rate) sclk 227 sound/soc/codecs/rl6231.c if (sclk <= 0 || rate <= 0) sclk 232 sound/soc/codecs/rl6231.c if (sclk == rate * pd[i]) sclk 29 sound/soc/codecs/rl6231.h int rl6231_get_clk_info(int sclk, int rate); sclk 1520 sound/soc/codecs/rt1011.c static int rt1011_get_clk_info(int sclk, int rate) sclk 1525 sound/soc/codecs/rt1011.c if (sclk <= 0 || rate <= 0) sclk 1530 sound/soc/codecs/rt1011.c if (sclk == rate * pd[i]) sclk 609 sound/soc/codecs/rt1305.c static int rt1305_get_clk_info(int sclk, int rate) sclk 614 sound/soc/codecs/rt1305.c if (sclk <= 0 || rate <= 0) sclk 619 sound/soc/codecs/rt1305.c if (sclk == rate * pd[i]) sclk 437 sound/soc/codecs/rt1308.c static int rt1308_get_clk_info(int sclk, int rate) sclk 442 sound/soc/codecs/rt1308.c if (sclk <= 0 || rate <= 0) sclk 447 sound/soc/codecs/rt1308.c if (sclk == rate * pd[i]) sclk 241 sound/soc/codecs/tas5086.c unsigned int mclk, sclk; sclk 307 sound/soc/codecs/tas5086.c priv->sclk = freq; sclk 394 sound/soc/codecs/tas5086.c (priv->sclk == 48 * priv->rate) ? sclk 47 sound/soc/intel/boards/kbl_rt5663_max98927.c struct clk *sclk; sclk 99 sound/soc/intel/boards/kbl_rt5663_max98927.c ret = clk_set_rate(priv->sclk, 3072000); sclk 107 sound/soc/intel/boards/kbl_rt5663_max98927.c ret = clk_prepare_enable(priv->sclk); sclk 115 sound/soc/intel/boards/kbl_rt5663_max98927.c clk_disable_unprepare(priv->sclk); sclk 984 sound/soc/intel/boards/kbl_rt5663_max98927.c ctx->sclk = devm_clk_get(&pdev->dev, "ssp1_sclk"); sclk 985 sound/soc/intel/boards/kbl_rt5663_max98927.c if (IS_ERR(ctx->sclk)) { sclk 986 sound/soc/intel/boards/kbl_rt5663_max98927.c ret = PTR_ERR(ctx->sclk); sclk 199 sound/soc/intel/skylake/skl-nhlt.c struct skl_ssp_clk *sclk, *sclkfs; sclk 210 sound/soc/intel/skylake/skl-nhlt.c sclk = &ssp_clks[SKL_SCLK_OFS]; sclk 248 sound/soc/intel/skylake/skl-nhlt.c (sclk[id].rate_cfg[j].rate != 0); j++) { sclk 249 sound/soc/intel/skylake/skl-nhlt.c if (sclk[id].rate_cfg[j].rate == rate) { sclk 279 sound/soc/intel/skylake/skl-nhlt.c sclk[id].rate_cfg[rate_index].rate = rate; sclk 280 sound/soc/intel/skylake/skl-nhlt.c sclk[id].rate_cfg[rate_index].config = fmt_cfg; sclk 283 sound/soc/intel/skylake/skl-nhlt.c sclk[id].parent_name = parent->name; sclk 20 sound/soc/meson/axg-tdm-formatter.c struct clk *sclk; sclk 103 sound/soc/meson/axg-tdm-formatter.c ret = clk_set_phase(formatter->sclk, invert ? 180 : 0); sclk 115 sound/soc/meson/axg-tdm-formatter.c ret = clk_prepare_enable(formatter->sclk); sclk 121 sound/soc/meson/axg-tdm-formatter.c clk_disable_unprepare(formatter->sclk); sclk 140 sound/soc/meson/axg-tdm-formatter.c clk_disable_unprepare(formatter->sclk); sclk 197 sound/soc/meson/axg-tdm-formatter.c ret = clk_set_parent(formatter->sclk_sel, ts->iface->sclk); sclk 292 sound/soc/meson/axg-tdm-formatter.c formatter->sclk = devm_clk_get(dev, "sclk"); sclk 293 sound/soc/meson/axg-tdm-formatter.c if (IS_ERR(formatter->sclk)) { sclk 294 sound/soc/meson/axg-tdm-formatter.c ret = PTR_ERR(formatter->sclk); sclk 274 sound/soc/meson/axg-tdm-interface.c ret = clk_set_rate(iface->sclk, srate); sclk 281 sound/soc/meson/axg-tdm-interface.c ret = clk_set_phase(iface->sclk, sclk 499 sound/soc/meson/axg-tdm-interface.c iface->sclk = devm_clk_get(dev, "sclk"); sclk 500 sound/soc/meson/axg-tdm-interface.c if (IS_ERR(iface->sclk)) { sclk 501 sound/soc/meson/axg-tdm-interface.c ret = PTR_ERR(iface->sclk); sclk 27 sound/soc/meson/axg-tdm.h struct clk *sclk; sclk 84 sound/soc/samsung/spdif.c struct clk *sclk; sclk 393 sound/soc/samsung/spdif.c spdif->sclk = devm_clk_get(&pdev->dev, "sclk_spdif"); sclk 394 sound/soc/samsung/spdif.c if (IS_ERR(spdif->sclk)) { sclk 399 sound/soc/samsung/spdif.c ret = clk_prepare_enable(spdif->sclk); sclk 449 sound/soc/samsung/spdif.c clk_disable_unprepare(spdif->sclk); sclk 467 sound/soc/samsung/spdif.c clk_disable_unprepare(spdif->sclk);