scl_data 2799 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); scl_data 2801 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); scl_data 2802 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); scl_data 2803 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); scl_data 2804 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value); scl_data 2805 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); scl_data 2853 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height); scl_data 2854 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width); scl_data 2857 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps); scl_data 2858 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps); scl_data 2860 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value); scl_data 2862 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); scl_data 2901 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); scl_data 2903 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); scl_data 2904 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); scl_data 2905 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); scl_data 2906 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value); scl_data 2907 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); scl_data 336 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; scl_data 337 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; scl_data 338 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; scl_data 339 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; scl_data 387 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; scl_data 388 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; scl_data 389 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; scl_data 390 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; scl_data 393 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; scl_data 394 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; scl_data 395 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; scl_data 396 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; scl_data 397 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; scl_data 398 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->scale_ratio_depth.vinit_c = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0; scl_data 401 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c switch (pipe->plane_res.scl_data.lb_params.depth) { scl_data 414 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.recout_width = pipe->plane_res.scl_data.recout.width; scl_data 415 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.recout_height = pipe->plane_res.scl_data.recout.height; scl_data 417 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.full_recout_width = pipe->plane_res.scl_data.recout.width; scl_data 418 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.full_recout_height = pipe->plane_res.scl_data.recout.height; scl_data 914 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->viewport_height[input_idx] = pipe->plane_res.scl_data.viewport.height; scl_data 915 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width; scl_data 916 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width; scl_data 917 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height; scl_data 920 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c int viewport_end = pipe->plane_res.scl_data.viewport.width scl_data 921 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + pipe->plane_res.scl_data.viewport.x; scl_data 922 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width scl_data 923 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + pipe->bottom_pipe->plane_res.scl_data.viewport.x; scl_data 927 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->bottom_pipe->plane_res.scl_data.viewport.x; scl_data 930 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->plane_res.scl_data.viewport.x; scl_data 932 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c int viewport_end = pipe->plane_res.scl_data.viewport.height scl_data 933 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + pipe->plane_res.scl_data.viewport.y; scl_data 934 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height scl_data 935 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + pipe->bottom_pipe->plane_res.scl_data.viewport.y; scl_data 939 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->bottom_pipe->plane_res.scl_data.viewport.y; scl_data 942 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c - pipe->plane_res.scl_data.viewport.y; scl_data 944 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width scl_data 945 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + pipe->bottom_pipe->plane_res.scl_data.recout.width; scl_data 949 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value scl_data 951 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value scl_data 954 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value scl_data 956 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value scl_data 983 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth); scl_data 984 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; scl_data 985 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; scl_data 986 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; scl_data 987 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; scl_data 447 drivers/gpu/drm/amd/display/dc/core/dc.c pipes->plane_res.scl_data.lb_params.depth, scl_data 551 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct scaler_data *data = &pipe_ctx->plane_res.scl_data; scl_data 666 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; scl_data 668 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x scl_data 672 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * scl_data 674 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > scl_data 676 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width = scl_data 678 drivers/gpu/drm/amd/display/dc/core/dc_resource.c - pipe_ctx->plane_res.scl_data.recout.x; scl_data 680 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; scl_data 682 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y scl_data 686 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * scl_data 688 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y > scl_data 690 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height = scl_data 692 drivers/gpu/drm/amd/display/dc/core/dc_resource.c - pipe_ctx->plane_res.scl_data.recout.y; scl_data 696 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += scl_data 697 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height / 2; scl_data 699 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height = scl_data 700 drivers/gpu/drm/amd/display/dc/core/dc_resource.c (pipe_ctx->plane_res.scl_data.recout.height + 1) / 2; scl_data 702 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.height /= 2; scl_data 704 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += scl_data 705 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width / 2; scl_data 707 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width = scl_data 708 drivers/gpu/drm/amd/display/dc/core/dc_resource.c (pipe_ctx->plane_res.scl_data.recout.width + 1) / 2; scl_data 710 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.width /= 2; scl_data 728 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( scl_data 731 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( scl_data 736 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; scl_data 738 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; scl_data 740 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( scl_data 741 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); scl_data 742 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( scl_data 743 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); scl_data 745 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; scl_data 746 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; scl_data 748 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8 scl_data 749 drivers/gpu/drm/amd/display/dc/core/dc_resource.c || pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) { scl_data 750 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2; scl_data 751 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2; scl_data 753 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate( scl_data 754 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz, 19); scl_data 755 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( scl_data 756 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert, 19); scl_data 757 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate( scl_data 758 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.horz_c, 19); scl_data 759 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate( scl_data 760 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.ratios.vert_c, 19); scl_data 847 drivers/gpu/drm/amd/display/dc/core/dc_resource.c struct scaler_data *data = &pipe_ctx->plane_res.scl_data; scl_data 972 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface( scl_data 979 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16) scl_data 988 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; scl_data 990 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left; scl_data 991 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top; scl_data 993 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right; scl_data 994 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; scl_data 999 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); scl_data 1003 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); scl_data 1007 drivers/gpu/drm/amd/display/dc/core/dc_resource.c are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport, scl_data 1008 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.recout)) { scl_data 1009 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.taps.v_taps = 1; scl_data 1010 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.taps.h_taps = 1; scl_data 1015 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; scl_data 1020 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &pipe_ctx->plane_res.scl_data, scl_data 1026 drivers/gpu/drm/amd/display/dc/core/dc_resource.c &pipe_ctx->plane_res.scl_data, scl_data 1039 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.height, scl_data 1040 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.width, scl_data 1041 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.x, scl_data 1042 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->plane_res.scl_data.viewport.y, scl_data 893 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c struct scaler_data *scl_data, scl_data 897 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c int pixel_width = scl_data->viewport.width; scl_data 901 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c (scl_data->viewport.width > scl_data->recout.width)) scl_data 902 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c pixel_width = scl_data->recout.width; scl_data 906 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->lb_params.depth, scl_data 922 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); scl_data 923 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); scl_data 924 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); scl_data 925 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); scl_data 927 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (!IDENTITY_RATIO(scl_data->ratios.vert)) { scl_data 930 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c && max_num_of_lines <= scl_data->taps.v_taps scl_data 931 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c && scl_data->taps.v_taps > 1) { scl_data 932 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.v_taps = max_num_of_lines - 1; scl_data 935 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (scl_data->taps.v_taps <= 1) scl_data 939 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (!IDENTITY_RATIO(scl_data->ratios.vert_c)) { scl_data 941 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (max_num_of_lines <= scl_data->taps.v_taps_c && scl_data->taps.v_taps_c > 1) { scl_data 942 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c scl_data->taps.v_taps_c = max_num_of_lines - 1; scl_data 945 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c if (scl_data->taps.v_taps_c <= 1) scl_data 494 drivers/gpu/drm/amd/display/dc/dce/dce_transform.h struct scaler_data *scl_data, scl_data 1198 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c switch (pipe_ctx->plane_res.scl_data.format) { scl_data 1248 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.depth, scl_data 1266 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c &pipe_ctx->plane_res.scl_data); scl_data 1419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; scl_data 2121 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; scl_data 2128 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; scl_data 2507 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; scl_data 2566 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.width, scl_data 2567 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.height, scl_data 2568 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.x, scl_data 2569 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.viewport.y, scl_data 2570 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.width, scl_data 2571 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.height, scl_data 2572 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.x, scl_data 2573 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.scl_data.recout.y); scl_data 2691 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .viewport = pipe_ctx->plane_res.scl_data.viewport, scl_data 2692 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, scl_data 2693 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, scl_data 50 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c const struct scaler_data *scl_data, scl_data 55 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; scl_data 56 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; scl_data 58 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c scl_data->viewport.width - scl_data->viewport.width % 2; scl_data 60 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c scl_data->viewport.height - scl_data->viewport.height % 2; scl_data 66 drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c if (scl_data->format == PIXEL_FORMAT_420BPP8) { scl_data 134 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c struct scaler_data *scl_data, scl_data 139 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->viewport.width > scl_data->recout.width) scl_data 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c pixel_width = scl_data->recout.width; scl_data 142 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c pixel_width = scl_data->viewport.width; scl_data 145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->format == PIXEL_FORMAT_FP16 && scl_data 147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->ratios.horz.value != dc_fixpt_one.value && scl_data 148 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->ratios.vert.value != dc_fixpt_one.value) scl_data 151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->viewport.width > scl_data->h_active && scl_data 153 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) scl_data 159 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->ratios.horz.value == (4ll << 32)) scl_data 160 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->ratios.horz.value--; scl_data 161 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->ratios.vert.value == (4ll << 32)) scl_data 162 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->ratios.vert.value--; scl_data 163 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->ratios.horz_c.value == (4ll << 32)) scl_data 164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->ratios.horz_c.value--; scl_data 165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (scl_data->ratios.vert_c.value == (4ll << 32)) scl_data 166 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->ratios.vert_c.value--; scl_data 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps = 4; scl_data 172 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps = in_taps->h_taps; scl_data 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.v_taps = 4; scl_data 176 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.v_taps = in_taps->v_taps; scl_data 178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.v_taps_c = 2; scl_data 180 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.v_taps_c = in_taps->v_taps_c; scl_data 182 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps_c = 2; scl_data 185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; scl_data 187 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps_c = in_taps->h_taps_c; scl_data 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (IDENTITY_RATIO(scl_data->ratios.horz)) scl_data 191 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps = 1; scl_data 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (IDENTITY_RATIO(scl_data->ratios.vert)) scl_data 193 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.v_taps = 1; scl_data 194 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (IDENTITY_RATIO(scl_data->ratios.horz_c)) scl_data 195 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.h_taps_c = 1; scl_data 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c if (IDENTITY_RATIO(scl_data->ratios.vert_c)) scl_data 197 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c scl_data->taps.v_taps_c = 1; scl_data 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); scl_data 1359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h struct scaler_data scl_data; scl_data 1390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h const struct scaler_data *scl_data, scl_data 1482 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h const struct scaler_data *scl_data); scl_data 300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c const struct scaler_data *scl_data, scl_data 307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; scl_data 308 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; scl_data 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 scl_data 316 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && scl_data->taps.h_taps_c < 3 scl_data 317 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); scl_data 318 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 scl_data 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && scl_data->taps.v_taps_c < 3 scl_data 320 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); scl_data 337 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->taps.h_taps, scl_data->ratios.horz); scl_data 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->taps.v_taps, scl_data->ratios.vert); scl_data 346 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->taps.h_taps_c, scl_data->ratios.horz_c); scl_data 348 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->taps.v_taps_c, scl_data->ratios.vert_c); scl_data 358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.h_taps, scl_data 364 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.v_taps, scl_data 371 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.h_taps_c, scl_data 376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp, scl_data->taps.v_taps_c, scl_data 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c const struct scaler_data *scl_data, scl_data 420 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c int line_size = scl_data->viewport.width < scl_data->recout.width ? scl_data 421 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->viewport.width : scl_data->recout.width; scl_data 422 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? scl_data 423 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data->viewport_c.width : scl_data->recout.width; scl_data 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth); scl_data 459 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (scl_data->lb_params.alpha_en scl_data 480 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c const struct scaler_data *scl_data) scl_data 483 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c int vtaps = scl_data->taps.v_taps; scl_data 484 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c int vtaps_c = scl_data->taps.v_taps_c; scl_data 485 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); scl_data 486 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c); scl_data 493 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c); scl_data 500 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c); scl_data 506 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (scl_data->format == PIXEL_FORMAT_420BPP8 scl_data 507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c || scl_data->format == PIXEL_FORMAT_420BPP10) { scl_data 509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c); scl_data 517 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c); scl_data 528 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c const struct scaler_data *scl_data) scl_data 533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); scl_data 534 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN scl_data 535 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && scl_data->format <= PIXEL_FORMAT_VIDEO_END; scl_data 537 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_overscan(dpp, scl_data); scl_data 539 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_otg_blank(dpp, scl_data); scl_data 546 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); scl_data 547 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); scl_data 570 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, scl_data 571 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, scl_data 572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, scl_data 573 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); scl_data 575 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); scl_data 667 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c const struct scaler_data *scl_data) scl_data 672 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); scl_data 673 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN scl_data 674 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c && scl_data->format <= PIXEL_FORMAT_VIDEO_END; scl_data 676 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) scl_data 681 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp->scl_data = *scl_data; scl_data 690 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_recout(dpp, &scl_data->recout); scl_data 695 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c MPC_WIDTH, scl_data->h_active, scl_data 697 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c MPC_HEIGHT, scl_data->v_active); scl_data 706 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); scl_data 707 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); scl_data 726 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_manual_ratio_init(dpp, scl_data); scl_data 730 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, scl_data 731 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, scl_data 732 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, scl_data 733 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); scl_data 735 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); scl_data 2031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c switch (pipe_ctx->plane_res.scl_data.format) { scl_data 2073 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c switch (top_pipe_ctx->plane_res.scl_data.format) { scl_data 2272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; scl_data 2273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; scl_data 2276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); scl_data 2334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c size.surface_size = pipe_ctx->plane_res.scl_data.viewport; scl_data 2358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->plane_res.scl_data.viewport, scl_data 2359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->plane_res.scl_data.viewport_c); scl_data 2962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .viewport = pipe_ctx->plane_res.scl_data.viewport, scl_data 2963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, scl_data 2964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, scl_data 2985 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width - scl_data 2986 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c (pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x; scl_data 2992 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pos_cpy.x > pipe_ctx->plane_res.scl_data.viewport.height) { scl_data 2993 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height; scl_data 2994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x; scl_data 2996 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x; scl_data 3002 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) { scl_data 3003 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width scl_data 3004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x; scl_data 3007 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x; scl_data 3008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width scl_data 3010 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width; scl_data 3013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y; scl_data 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c const struct scaler_data *scl_data, scl_data 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c int line_size = scl_data->viewport.width < scl_data->recout.width ? scl_data 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->viewport.width : scl_data->recout.width; scl_data 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? scl_data 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->viewport_c.width : scl_data->recout.width; scl_data 310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->lb_params.alpha_en scl_data 376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c struct scaler_data *scl_data, scl_data 381 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->viewport.width > scl_data->recout.width) scl_data 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c pixel_width = scl_data->recout.width; scl_data 384 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c pixel_width = scl_data->viewport.width; scl_data 387 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->viewport.width != scl_data->h_active && scl_data 388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->viewport.height != scl_data->v_active && scl_data 390 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->format == PIXEL_FORMAT_FP16) scl_data 393 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->viewport.width > scl_data->h_active && scl_data 395 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) scl_data 401 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->ratios.horz.value == (8ll << 32)) scl_data 402 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->ratios.horz.value--; scl_data 403 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->ratios.vert.value == (8ll << 32)) scl_data 404 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->ratios.vert.value--; scl_data 405 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->ratios.horz_c.value == (8ll << 32)) scl_data 406 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->ratios.horz_c.value--; scl_data 407 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (scl_data->ratios.vert_c.value == (8ll << 32)) scl_data 408 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->ratios.vert_c.value--; scl_data 412 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (dc_fixpt_ceil(scl_data->ratios.horz) > 4) scl_data 413 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = 8; scl_data 415 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = 4; scl_data 417 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = in_taps->h_taps; scl_data 419 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (dc_fixpt_ceil(scl_data->ratios.vert) > 4) scl_data 420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps = 8; scl_data 422 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps = 4; scl_data 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps = in_taps->v_taps; scl_data 426 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 4) scl_data 427 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps_c = 4; scl_data 429 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps_c = 2; scl_data 431 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps_c = in_taps->v_taps_c; scl_data 433 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 4) scl_data 434 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps_c = 4; scl_data 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps_c = 2; scl_data 439 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; scl_data 441 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps_c = in_taps->h_taps_c; scl_data 444 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (IDENTITY_RATIO(scl_data->ratios.horz)) scl_data 445 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps = 1; scl_data 446 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (IDENTITY_RATIO(scl_data->ratios.vert)) scl_data 447 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps = 1; scl_data 448 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (IDENTITY_RATIO(scl_data->ratios.horz_c)) scl_data 449 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.h_taps_c = 1; scl_data 450 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c if (IDENTITY_RATIO(scl_data->ratios.vert_c)) scl_data 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c scl_data->taps.v_taps_c = 1; scl_data 641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct scaler_data scl_data; scl_data 672 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h const struct scaler_data *scl_data, scl_data 696 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h struct scaler_data *scl_data, scl_data 1752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; scl_data 1769 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c sd = &next_odm_pipe->plane_res.scl_data; scl_data 2072 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; scl_data 2103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width; scl_data 2105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height; scl_data 2108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; scl_data 2110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height; scl_data 258 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct scaler_data scl_data; scl_data 123 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h const struct scaler_data *scl_data); scl_data 132 drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h struct scaler_data *scl_data, scl_data 188 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h const struct scaler_data *scl_data); scl_data 197 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h struct scaler_data *scl_data, scl_data 299 drivers/gpu/drm/amd/display/dc/inc/hw/transform.h const struct scaler_data *scl_data,