scdc 1186 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!display->hdmi.scdc.supported || scdc 1187 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c !display->hdmi.scdc.scrambling.supported) scdc 1194 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c if (!display->hdmi.scdc.scrambling.low_rates && scdc 1751 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_info->scdc.scrambling.low_rates)) ? scdc 1819 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c hdmi_info->scdc.scrambling.low_rates) { scdc 4456 drivers/gpu/drm/drm_edid.c hdmi->scdc.supported = true; scdc 4458 drivers/gpu/drm/drm_edid.c hdmi->scdc.read_request = true; scdc 4473 drivers/gpu/drm/drm_edid.c struct drm_scdc *scdc = &hdmi->scdc; scdc 4481 drivers/gpu/drm/drm_edid.c if (scdc->supported) { scdc 4482 drivers/gpu/drm/drm_edid.c scdc->scrambling.supported = true; scdc 4486 drivers/gpu/drm/drm_edid.c scdc->scrambling.low_rates = true; scdc 4999 drivers/gpu/drm/drm_edid.c return connector->display_info.hdmi.scdc.supported || scdc 2302 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; scdc 2401 drivers/gpu/drm/i915/display/intel_hdmi.c if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || scdc 2403 drivers/gpu/drm/i915/display/intel_hdmi.c if (scdc->scrambling.low_rates) scdc 2852 drivers/gpu/drm/i915/display/intel_hdmi.c &connector->display_info.hdmi.scdc.scrambling; scdc 614 drivers/gpu/drm/nouveau/dispnv50/disp.c if (hdmi->scdc.scrambling.supported) { scdc 617 drivers/gpu/drm/nouveau/dispnv50/disp.c hdmi->scdc.scrambling.low_rates; scdc 620 drivers/gpu/drm/nouveau/dispnv50/disp.c args.pwr.scdc = scdc 635 drivers/gpu/drm/nouveau/dispnv50/disp.c if (!hdmi->scdc.scrambling.supported) scdc 74 drivers/gpu/drm/nouveau/include/nvif/cl5070.h __u8 scdc; scdc 1010 drivers/gpu/drm/nouveau/nouveau_connector.c info->hdmi.scdc.scrambling.supported ? scdc 27 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c gm200_hdmi_scdc(struct nvkm_ior *ior, int head, u8 scdc) scdc 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c const u32 ctrl = scdc & 0x3; scdc 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigm200.c ior->tmds.high_speed = !!(scdc & 0x2); scdc 69 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.h void (*scdc)(struct nvkm_ior *, int head, u8 scdc); scdc 182 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c args->v0.scdc); scdc 207 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c if (outp->ior->func->hdmi.scdc) scdc 208 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c outp->ior->func->hdmi.scdc( scdc 209 drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv50.c outp->ior, hidx, args->v0.scdc); scdc 102 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm200.c .scdc = gm200_hdmi_scdc, scdc 91 drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgv100.c .scdc = gm200_hdmi_scdc, scdc 75 drivers/gpu/drm/nouveau/nvkm/engine/disp/sortu102.c .scdc = gm200_hdmi_scdc, scdc 430 drivers/gpu/drm/tegra/sor.c struct delayed_work scdc; scdc 2328 drivers/gpu/drm/tegra/sor.c cancel_delayed_work_sync(&sor->scdc); scdc 2355 drivers/gpu/drm/tegra/sor.c struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); scdc 2363 drivers/gpu/drm/tegra/sor.c schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); scdc 2368 drivers/gpu/drm/tegra/sor.c struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; scdc 2373 drivers/gpu/drm/tegra/sor.c if (mode->clock >= 340000 && scdc->supported) { scdc 2374 drivers/gpu/drm/tegra/sor.c schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); scdc 3007 drivers/gpu/drm/tegra/sor.c INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); scdc 187 include/drm/drm_connector.h struct drm_scdc scdc;