scatter_gather_page_width 502 drivers/gpu/drm/amd/display/dc/calcs/calcs_logger.h i, bw_fixed_to_int(data->scatter_gather_page_width[i])); scatter_gather_page_width 996 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_div(bw_int_to_fixed(4096), bw_int_to_fixed(data->bytes_per_pixel[i])); scatter_gather_page_width 1005 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_int_to_fixed(32); scatter_gather_page_width 1009 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_int_to_fixed(64); scatter_gather_page_width 1013 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_int_to_fixed(64); scatter_gather_page_width 1024 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_int_to_fixed(32); scatter_gather_page_width 1028 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_int_to_fixed(32); scatter_gather_page_width 1032 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->scatter_gather_page_width[i] = bw_int_to_fixed(64); scatter_gather_page_width 1039 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->pte_request_per_chunk[i] = bw_div(bw_div(bw_int_to_fixed(dceip->chunk_width), data->scatter_gather_page_width[i]), data->useful_pte_per_pte_request); scatter_gather_page_width 1099 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c data->bytes_per_page_close_open = bw_mul(data->lines_interleaved_in_mem_access[i], bw_max2(bw_mul(bw_mul(bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->tile_width_in_pixels), bw_int_to_fixed(vbios->number_of_dram_banks)), bw_int_to_fixed(data->number_of_dram_channels)), bw_mul(bw_int_to_fixed(data->bytes_per_pixel[i]), data->scatter_gather_page_width[i]))); scatter_gather_page_width 435 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces];