scaler_offset     205 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		u32 scaler_offset, u32 scaler_version,
scaler_offset     241 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		_dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
scaler_offset     247 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 								scaler_offset);
scaler_offset     255 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		DPU_REG_WRITE(c, QSEED3_PHASE_INIT + scaler_offset, phase_init);
scaler_offset     257 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_H + scaler_offset,
scaler_offset     259 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		DPU_REG_WRITE(c, QSEED3_PHASE_INIT_Y_V + scaler_offset,
scaler_offset     261 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_H + scaler_offset,
scaler_offset     263 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		DPU_REG_WRITE(c, QSEED3_PHASE_INIT_UV_V + scaler_offset,
scaler_offset     267 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_H + scaler_offset,
scaler_offset     270 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_PHASE_STEP_Y_V + scaler_offset,
scaler_offset     273 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_H + scaler_offset,
scaler_offset     276 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_PHASE_STEP_UV_V + scaler_offset,
scaler_offset     279 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_PRELOAD + scaler_offset, preload);
scaler_offset     281 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_SRC_SIZE_Y_RGB_A + scaler_offset, src_y_rgb);
scaler_offset     283 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_SRC_SIZE_UV + scaler_offset, src_uv);
scaler_offset     285 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
scaler_offset     299 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	DPU_REG_WRITE(c, QSEED3_OP_MODE + scaler_offset, op_mode);
scaler_offset     303 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			u32 scaler_offset)
scaler_offset     305 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	return DPU_REG_READ(c, QSEED3_HW_VERSION + scaler_offset);
scaler_offset     313 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 		u32 scaler_offset, u32 scaler_version,
scaler_offset     317 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 		u32 scaler_offset);