scaler3_cfg       403 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	struct dpu_hw_scaler3_cfg *scaler3_cfg = scaler_cfg;
scaler3_cfg       407 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 		|| !scaler3_cfg || !ctx || !ctx->cap || !ctx->cap->sblk)
scaler3_cfg       410 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c 	dpu_hw_setup_scaler3(&ctx->hw, scaler3_cfg, idx,
scaler3_cfg        85 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
scaler3_cfg       100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	lut_flags = (unsigned long) scaler3_cfg->lut_flag;
scaler3_cfg       102 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->dir_len == QSEED3_DIR_LUT_SIZE)) {
scaler3_cfg       103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		lut[0] = scaler3_cfg->dir_lut;
scaler3_cfg       107 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->y_rgb_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
scaler3_cfg       108 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
scaler3_cfg       109 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		lut[1] = scaler3_cfg->cir_lut +
scaler3_cfg       110 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->y_rgb_cir_lut_idx * QSEED3_LUT_SIZE;
scaler3_cfg       114 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->uv_cir_lut_idx < QSEED3_CIRCULAR_LUTS) &&
scaler3_cfg       115 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->cir_len == QSEED3_CIR_LUT_SIZE)) {
scaler3_cfg       116 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		lut[2] = scaler3_cfg->cir_lut +
scaler3_cfg       117 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->uv_cir_lut_idx * QSEED3_LUT_SIZE;
scaler3_cfg       121 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->y_rgb_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
scaler3_cfg       122 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
scaler3_cfg       123 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		lut[3] = scaler3_cfg->sep_lut +
scaler3_cfg       124 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->y_rgb_sep_lut_idx * QSEED3_LUT_SIZE;
scaler3_cfg       128 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->uv_sep_lut_idx < QSEED3_SEPARABLE_LUTS) &&
scaler3_cfg       129 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		(scaler3_cfg->sep_len == QSEED3_SEP_LUT_SIZE)) {
scaler3_cfg       130 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		lut[4] = scaler3_cfg->sep_lut +
scaler3_cfg       131 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->uv_sep_lut_idx * QSEED3_LUT_SIZE;
scaler3_cfg       204 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		struct dpu_hw_scaler3_cfg *scaler3_cfg,
scaler3_cfg       211 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	if (!scaler3_cfg->enable)
scaler3_cfg       215 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
scaler3_cfg       219 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
scaler3_cfg       222 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	op_mode |= (scaler3_cfg->blend_cfg & 1) << 31;
scaler3_cfg       223 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	op_mode |= (scaler3_cfg->dir_en) ? BIT(4) : 0;
scaler3_cfg       226 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->preload_x[0] & 0x7F) << 0) |
scaler3_cfg       227 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->preload_y[0] & 0x7F) << 8) |
scaler3_cfg       228 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->preload_x[1] & 0x7F) << 16) |
scaler3_cfg       229 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->preload_y[1] & 0x7F) << 24);
scaler3_cfg       231 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	src_y_rgb = (scaler3_cfg->src_width[0] & 0x1FFFF) |
scaler3_cfg       232 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->src_height[0] & 0x1FFFF) << 16);
scaler3_cfg       234 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	src_uv = (scaler3_cfg->src_width[1] & 0x1FFFF) |
scaler3_cfg       235 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->src_height[1] & 0x1FFFF) << 16);
scaler3_cfg       237 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	dst = (scaler3_cfg->dst_width & 0x1FFFF) |
scaler3_cfg       238 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		((scaler3_cfg->dst_height & 0x1FFFF) << 16);
scaler3_cfg       240 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	if (scaler3_cfg->de.enable) {
scaler3_cfg       241 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		_dpu_hw_setup_scaler3_de(c, &scaler3_cfg->de, scaler_offset);
scaler3_cfg       245 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 	if (scaler3_cfg->lut_flag)
scaler3_cfg       246 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		_dpu_hw_setup_scaler3_lut(c, scaler3_cfg,
scaler3_cfg       251 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			((scaler3_cfg->init_phase_x[0] & 0x3F) << 0) |
scaler3_cfg       252 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			((scaler3_cfg->init_phase_y[0] & 0x3F) << 8) |
scaler3_cfg       253 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			((scaler3_cfg->init_phase_x[1] & 0x3F) << 16) |
scaler3_cfg       254 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			((scaler3_cfg->init_phase_y[1] & 0x3F) << 24);
scaler3_cfg       258 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->init_phase_x[0] & 0x1FFFFF);
scaler3_cfg       260 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->init_phase_y[0] & 0x1FFFFF);
scaler3_cfg       262 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->init_phase_x[1] & 0x1FFFFF);
scaler3_cfg       264 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			scaler3_cfg->init_phase_y[1] & 0x1FFFFF);
scaler3_cfg       268 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		scaler3_cfg->phase_step_x[0] & 0xFFFFFF);
scaler3_cfg       271 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		scaler3_cfg->phase_step_y[0] & 0xFFFFFF);
scaler3_cfg       274 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		scaler3_cfg->phase_step_x[1] & 0xFFFFFF);
scaler3_cfg       277 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 		scaler3_cfg->phase_step_y[1] & 0xFFFFFF);
scaler3_cfg       294 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x1) << 30;
scaler3_cfg       296 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c 			op_mode |= (scaler3_cfg->alpha_filter_cfg & 0x3) << 29;
scaler3_cfg       312 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h 		struct dpu_hw_scaler3_cfg *scaler3_cfg,
scaler3_cfg       561 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			&pstate->scaler3_cfg, fmt,
scaler3_cfg       620 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					&pstate->scaler3_cfg);
scaler3_cfg      1031 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pstate->scaler3_cfg);
scaler3_cfg        38 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h 	struct dpu_hw_scaler3_cfg scaler3_cfg;