scale_cfg 443 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c struct dpu_hw_scaler3_cfg *scale_cfg, scale_cfg 449 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c memset(scale_cfg, 0, sizeof(*scale_cfg)); scale_cfg 452 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_0] = scale_cfg 454 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_0] = scale_cfg 458 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] = scale_cfg 459 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v; scale_cfg 460 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] = scale_cfg 461 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h; scale_cfg 463 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_2] = scale_cfg 464 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2]; scale_cfg 465 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_2] = scale_cfg 466 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2]; scale_cfg 468 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_3] = scale_cfg 469 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_x[DPU_SSPP_COMP_0]; scale_cfg 470 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_3] = scale_cfg 471 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->phase_step_y[DPU_SSPP_COMP_0]; scale_cfg 474 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->src_width[i] = src_w; scale_cfg 475 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->src_height[i] = src_h; scale_cfg 477 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->src_width[i] /= chroma_subsmpl_h; scale_cfg 478 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->src_height[i] /= chroma_subsmpl_v; scale_cfg 480 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H; scale_cfg 481 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; scale_cfg 483 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->src_height[i]; scale_cfg 485 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->src_width[i]; scale_cfg 491 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->dst_width = dst_w; scale_cfg 492 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->dst_height = dst_h; scale_cfg 493 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL; scale_cfg 494 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->uv_filter_cfg = DPU_SCALE_BIL; scale_cfg 495 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL; scale_cfg 496 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->lut_flag = 0; scale_cfg 497 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->blend_cfg = 1; scale_cfg 498 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c scale_cfg->enable = 1;