SDR0 172 arch/powerpc/platforms/4xx/msi.c mtdcri(SDR0, *sdr_addr, upper_32_bits(res.start)); /*HIGH addr */ SDR0 173 arch/powerpc/platforms/4xx/msi.c mtdcri(SDR0, *sdr_addr + 1, lower_32_bits(res.start)); /* Low addr */ SDR0 673 arch/powerpc/platforms/4xx/pci.c val = mfdcri(SDR0, port->sdr_base + sdr_offset); SDR0 735 arch/powerpc/platforms/4xx/pci.c if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { SDR0 743 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); SDR0 744 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); SDR0 745 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); SDR0 748 arch/powerpc/platforms/4xx/pci.c valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET); SDR0 749 arch/powerpc/platforms/4xx/pci.c valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET); SDR0 750 arch/powerpc/platforms/4xx/pci.c valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET); SDR0 809 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); SDR0 815 arch/powerpc/platforms/4xx/pci.c if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { SDR0 818 arch/powerpc/platforms/4xx/pci.c mfdcri(SDR0, PESDR0_PLLLCT2)); SDR0 823 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); SDR0 827 arch/powerpc/platforms/4xx/pci.c if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { SDR0 857 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); SDR0 858 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); SDR0 860 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); SDR0 861 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); SDR0 862 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); SDR0 863 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); SDR0 864 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); SDR0 866 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, SDR0 868 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, SDR0 870 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, SDR0 872 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, SDR0 875 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, SDR0 965 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); SDR0 966 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); SDR0 967 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); SDR0 971 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); SDR0 972 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); SDR0 973 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); SDR0 975 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); SDR0 979 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); SDR0 980 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); SDR0 981 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); SDR0 982 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); SDR0 983 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); SDR0 984 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); SDR0 985 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); SDR0 986 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); SDR0 987 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); SDR0 988 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); SDR0 989 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); SDR0 990 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); SDR0 992 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); SDR0 996 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, SDR0 997 arch/powerpc/platforms/4xx/pci.c mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | SDR0 1004 arch/powerpc/platforms/4xx/pci.c while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) SDR0 1008 arch/powerpc/platforms/4xx/pci.c while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) SDR0 1013 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, SDR0 1014 arch/powerpc/platforms/4xx/pci.c (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & SDR0 1070 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); SDR0 1080 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); SDR0 1081 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); SDR0 1082 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); SDR0 1084 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); SDR0 1085 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); SDR0 1086 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); SDR0 1088 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); SDR0 1090 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); SDR0 1092 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, SDR0 1093 arch/powerpc/platforms/4xx/pci.c mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | SDR0 1102 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, SDR0 1103 arch/powerpc/platforms/4xx/pci.c (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & SDR0 1123 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); SDR0 1124 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); SDR0 1125 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); SDR0 1126 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); SDR0 1127 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); SDR0 1128 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); SDR0 1129 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); SDR0 1130 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); SDR0 1132 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); SDR0 1133 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); SDR0 1134 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); SDR0 1135 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); SDR0 1137 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); SDR0 1138 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); SDR0 1139 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); SDR0 1140 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); SDR0 1143 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); SDR0 1144 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); SDR0 1145 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); SDR0 1146 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); SDR0 1147 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); SDR0 1148 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); SDR0 1149 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); SDR0 1150 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); SDR0 1152 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); SDR0 1153 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); SDR0 1154 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); SDR0 1155 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); SDR0 1157 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); SDR0 1158 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); SDR0 1159 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); SDR0 1160 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); SDR0 1163 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); SDR0 1164 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); SDR0 1165 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); SDR0 1168 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); SDR0 1169 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); SDR0 1170 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); SDR0 1173 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130); SDR0 1174 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130); SDR0 1179 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); SDR0 1182 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR0_460SX_RCSSET, SDR0 1184 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR1_460SX_RCSSET, SDR0 1186 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, PESDR2_460SX_RCSSET, SDR0 1195 arch/powerpc/platforms/4xx/pci.c if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == SDR0 1210 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, SDR0 1213 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, SDR0 1216 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, SDR0 1281 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000); SDR0 1286 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000); SDR0 1288 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000); SDR0 1292 arch/powerpc/platforms/4xx/pci.c while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000)) SDR0 1296 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000); SDR0 1308 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, SDR0 1311 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); SDR0 1312 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); SDR0 1313 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000); SDR0 1314 arch/powerpc/platforms/4xx/pci.c mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003); SDR0 1323 arch/powerpc/platforms/4xx/pci.c val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP); SDR0 1542 arch/powerpc/platforms/4xx/pci.c dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); SDR0 1388 drivers/crypto/amcc/crypto4xx_core.c mtdcri(SDR0, PPC460EX_SDR0_SRST, SDR0 1389 drivers/crypto/amcc/crypto4xx_core.c mfdcri(SDR0, PPC460EX_SDR0_SRST) | PPC460EX_CE_RESET); SDR0 1390 drivers/crypto/amcc/crypto4xx_core.c mtdcri(SDR0, PPC460EX_SDR0_SRST, SDR0 1391 drivers/crypto/amcc/crypto4xx_core.c mfdcri(SDR0, PPC460EX_SDR0_SRST) & ~PPC460EX_CE_RESET); SDR0 1394 drivers/crypto/amcc/crypto4xx_core.c mtdcri(SDR0, PPC405EX_SDR0_SRST, SDR0 1395 drivers/crypto/amcc/crypto4xx_core.c mfdcri(SDR0, PPC405EX_SDR0_SRST) | PPC405EX_CE_RESET); SDR0 1396 drivers/crypto/amcc/crypto4xx_core.c mtdcri(SDR0, PPC405EX_SDR0_SRST, SDR0 1397 drivers/crypto/amcc/crypto4xx_core.c mfdcri(SDR0, PPC405EX_SDR0_SRST) & ~PPC405EX_CE_RESET); SDR0 1401 drivers/crypto/amcc/crypto4xx_core.c mtdcri(SDR0, PPC460SX_SDR0_SRST, SDR0 1402 drivers/crypto/amcc/crypto4xx_core.c mfdcri(SDR0, PPC460SX_SDR0_SRST) | PPC460SX_CE_RESET); SDR0 1403 drivers/crypto/amcc/crypto4xx_core.c mtdcri(SDR0, PPC460SX_SDR0_SRST, SDR0 1404 drivers/crypto/amcc/crypto4xx_core.c mfdcri(SDR0, PPC460SX_SDR0_SRST) & ~PPC460SX_CE_RESET); SDR0 4469 drivers/dma/ppc4xx/adma.c mtdcri(SDR0, DCRN_SDR0_SRST, DCRN_SDR0_SRST_I2ODMA); SDR0 4470 drivers/dma/ppc4xx/adma.c mtdcri(SDR0, DCRN_SDR0_SRST, 0); SDR0 142 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_MFR, SDR0 151 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_MFR, SDR0 375 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_ETH_CFG, SDR0 379 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_ETH_CFG, SDR0 401 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_ETH_CFG, SDR0 2729 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); SDR0 2737 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS); SDR0 2800 drivers/net/ethernet/ibm/emac/core.c dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0); SDR0 283 drivers/net/ethernet/ibm/emac/mal.c mtdcri(SDR0, DCRN_SDR_ICINTSTAT, SDR0 284 drivers/net/ethernet/ibm/emac/mal.c (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX)); SDR0 303 drivers/net/ethernet/ibm/emac/mal.c mtdcri(SDR0, DCRN_SDR_ICINTSTAT, SDR0 304 drivers/net/ethernet/ibm/emac/mal.c (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX)); SDR0 359 drivers/spi/spi-ppc4xx.c dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);