SDMA0_BASE         45 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
SDMA0_BASE         48 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
SDMA0_BASE         47 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c 		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
SDMA0_BASE        135 drivers/gpu/drm/amd/include/arct_ip_offset.h static const struct IP_BASE SDMA0_BASE            ={ { { { 0x00001260, 0x00012540, 0x0040A800, 0, 0, 0 } },
SDMA0_BASE        186 drivers/gpu/drm/amd/include/renoir_ip_offset.h static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0x0240A800, 0, 0, 0 } },
SDMA0_BASE        168 drivers/gpu/drm/amd/include/vega10_ip_offset.h static const struct IP_BASE SDMA0_BASE			= { { { { 0x00001260, 0, 0, 0, 0 } },
SDMA0_BASE        111 drivers/gpu/drm/amd/include/vega20_ip_offset.h static const struct IP_BASE SDMA0_BASE            ={ { { { 0x00001260, 0, 0, 0, 0, 0 } },