saved_lpr0        412 arch/arm/mach-at91/pm.c 	u32 saved_lpr0, saved_lpr1 = 0;
saved_lpr0        434 arch/arm/mach-at91/pm.c 	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
saved_lpr0        435 arch/arm/mach-at91/pm.c 	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
saved_lpr0        446 arch/arm/mach-at91/pm.c 	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
saved_lpr0        456 arch/arm/mach-at91/pm.c 	u32 saved_lpr0;
saved_lpr0        458 arch/arm/mach-at91/pm.c 	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
saved_lpr0        459 arch/arm/mach-at91/pm.c 	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
saved_lpr0        466 arch/arm/mach-at91/pm.c 	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
saved_lpr0        475 arch/arm/mach-at91/pm.c 	u32 saved_lpr0, saved_lpr1 = 0;
saved_lpr0        483 arch/arm/mach-at91/pm.c 	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
saved_lpr0        484 arch/arm/mach-at91/pm.c 	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
saved_lpr0        494 arch/arm/mach-at91/pm.c 	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);