sarea_priv        358 drivers/gpu/drm/i810/i810_dma.c 	dev_priv->sarea_priv = (drm_i810_sarea_t *)
sarea_priv        564 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        565 drivers/gpu/drm/i810/i810_dma.c 	unsigned int dirty = sarea_priv->dirty;
sarea_priv        570 drivers/gpu/drm/i810/i810_dma.c 		i810EmitDestVerified(dev, sarea_priv->BufferState);
sarea_priv        571 drivers/gpu/drm/i810/i810_dma.c 		sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
sarea_priv        575 drivers/gpu/drm/i810/i810_dma.c 		i810EmitContextVerified(dev, sarea_priv->ContextState);
sarea_priv        576 drivers/gpu/drm/i810/i810_dma.c 		sarea_priv->dirty &= ~I810_UPLOAD_CTX;
sarea_priv        580 drivers/gpu/drm/i810/i810_dma.c 		i810EmitTexVerified(dev, sarea_priv->TexState[0]);
sarea_priv        581 drivers/gpu/drm/i810/i810_dma.c 		sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
sarea_priv        585 drivers/gpu/drm/i810/i810_dma.c 		i810EmitTexVerified(dev, sarea_priv->TexState[1]);
sarea_priv        586 drivers/gpu/drm/i810/i810_dma.c 		sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
sarea_priv        597 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        598 drivers/gpu/drm/i810/i810_dma.c 	int nbox = sarea_priv->nbox;
sarea_priv        599 drivers/gpu/drm/i810/i810_dma.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        670 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        671 drivers/gpu/drm/i810/i810_dma.c 	int nbox = sarea_priv->nbox;
sarea_priv        672 drivers/gpu/drm/i810/i810_dma.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        718 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        719 drivers/gpu/drm/i810/i810_dma.c 	struct drm_clip_rect *box = sarea_priv->boxes;
sarea_priv        720 drivers/gpu/drm/i810/i810_dma.c 	int nbox = sarea_priv->nbox;
sarea_priv        734 drivers/gpu/drm/i810/i810_dma.c 	if (sarea_priv->dirty)
sarea_priv        738 drivers/gpu/drm/i810/i810_dma.c 		unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
sarea_priv        801 drivers/gpu/drm/i810/i810_dma.c 		  dev_priv->sarea_priv->pf_current_page);
sarea_priv        835 drivers/gpu/drm/i810/i810_dma.c 	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
sarea_priv        935 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
sarea_priv        936 drivers/gpu/drm/i810/i810_dma.c 	    dev_priv->sarea_priv;
sarea_priv        951 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->last_enqueue = dev_priv->counter - 1;
sarea_priv        952 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->last_dispatch = (int)hw_status[5];
sarea_priv        989 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
sarea_priv        990 drivers/gpu/drm/i810/i810_dma.c 	    dev_priv->sarea_priv;
sarea_priv        992 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->last_dispatch = (int)hw_status[5];
sarea_priv       1003 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
sarea_priv       1004 drivers/gpu/drm/i810/i810_dma.c 	    dev_priv->sarea_priv;
sarea_priv       1015 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->last_dispatch = (int)hw_status[5];
sarea_priv       1039 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv       1054 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->dirty = 0x7f;
sarea_priv       1098 drivers/gpu/drm/i810/i810_dma.c 	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
sarea_priv       1099 drivers/gpu/drm/i810/i810_dma.c 	    dev_priv->sarea_priv;
sarea_priv       1110 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->last_enqueue = dev_priv->counter - 1;
sarea_priv       1111 drivers/gpu/drm/i810/i810_dma.c 	sarea_priv->last_dispatch = (int)hw_status[5];
sarea_priv       1167 drivers/gpu/drm/i810/i810_dma.c 	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
sarea_priv         87 drivers/gpu/drm/i810/i810_drv.h 	drm_i810_sarea_t *sarea_priv;
sarea_priv         77 drivers/gpu/drm/mga/mga_dma.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv         88 drivers/gpu/drm/mga/mga_dma.c 	sarea_priv->last_wrap = 0;
sarea_priv        201 drivers/gpu/drm/mga/mga_dma.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        205 drivers/gpu/drm/mga/mga_dma.c 	sarea_priv->last_wrap++;
sarea_priv        206 drivers/gpu/drm/mga/mga_dma.c 	DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
sarea_priv        230 drivers/gpu/drm/mga/mga_dma.c 		 dev_priv->sarea_priv->last_dispatch,
sarea_priv        332 drivers/gpu/drm/mga/mga_dma.c 	wrap = dev_priv->sarea_priv->last_wrap;
sarea_priv        875 drivers/gpu/drm/mga/mga_dma.c 	dev_priv->sarea_priv =
sarea_priv        929 drivers/gpu/drm/mga/mga_dma.c 	dev_priv->sarea_priv->last_wrap = 0;
sarea_priv        930 drivers/gpu/drm/mga/mga_dma.c 	dev_priv->sarea_priv->last_frame.head = 0;
sarea_priv        931 drivers/gpu/drm/mga/mga_dma.c 	dev_priv->sarea_priv->last_frame.wrap = 0;
sarea_priv        992 drivers/gpu/drm/mga/mga_dma.c 		dev_priv->sarea_priv = NULL;
sarea_priv         94 drivers/gpu/drm/mga/mga_drv.h 	drm_mga_sarea_t *sarea_priv;
sarea_priv        372 drivers/gpu/drm/mga/mga_drv.h 		entry->age.wrap = dev_priv->sarea_priv->last_wrap;	\
sarea_priv         44 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv         45 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv         68 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv         69 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv         91 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv         92 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        118 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        119 drivers/gpu/drm/mga/mga_state.c 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
sarea_priv        146 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        147 drivers/gpu/drm/mga/mga_state.c 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[0];
sarea_priv        186 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        187 drivers/gpu/drm/mga/mga_state.c 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[1];
sarea_priv        225 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        226 drivers/gpu/drm/mga/mga_state.c 	unsigned int pipe = sarea_priv->warp_pipe;
sarea_priv        252 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        253 drivers/gpu/drm/mga/mga_state.c 	unsigned int pipe = sarea_priv->warp_pipe;
sarea_priv        329 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        330 drivers/gpu/drm/mga/mga_state.c 	unsigned int dirty = sarea_priv->dirty;
sarea_priv        332 drivers/gpu/drm/mga/mga_state.c 	if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
sarea_priv        334 drivers/gpu/drm/mga/mga_state.c 		dev_priv->warp_pipe = sarea_priv->warp_pipe;
sarea_priv        339 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
sarea_priv        344 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
sarea_priv        350 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        351 drivers/gpu/drm/mga/mga_state.c 	unsigned int dirty = sarea_priv->dirty;
sarea_priv        352 drivers/gpu/drm/mga/mga_state.c 	int multitex = sarea_priv->warp_pipe & MGA_T2;
sarea_priv        354 drivers/gpu/drm/mga/mga_state.c 	if (sarea_priv->warp_pipe != dev_priv->warp_pipe) {
sarea_priv        356 drivers/gpu/drm/mga/mga_state.c 		dev_priv->warp_pipe = sarea_priv->warp_pipe;
sarea_priv        361 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->dirty &= ~MGA_UPLOAD_CONTEXT;
sarea_priv        366 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->dirty &= ~MGA_UPLOAD_TEX0;
sarea_priv        371 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->dirty &= ~MGA_UPLOAD_TEX1;
sarea_priv        383 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        384 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        402 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        403 drivers/gpu/drm/mga/mga_state.c 	drm_mga_texture_regs_t *tex = &sarea_priv->tex_state[unit];
sarea_priv        419 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        420 drivers/gpu/drm/mga/mga_state.c 	unsigned int dirty = sarea_priv->dirty;
sarea_priv        423 drivers/gpu/drm/mga/mga_state.c 	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
sarea_priv        424 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
sarea_priv        437 drivers/gpu/drm/mga/mga_state.c 			ret |= (sarea_priv->warp_pipe > MGA_MAX_G400_PIPES);
sarea_priv        440 drivers/gpu/drm/mga/mga_state.c 			ret |= (sarea_priv->warp_pipe > MGA_MAX_G200_PIPES);
sarea_priv        483 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        484 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        485 drivers/gpu/drm/mga/mga_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        486 drivers/gpu/drm/mga/mga_state.c 	int nbox = sarea_priv->nbox;
sarea_priv        571 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        572 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        573 drivers/gpu/drm/mga/mga_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        574 drivers/gpu/drm/mga/mga_state.c 	int nbox = sarea_priv->nbox;
sarea_priv        579 drivers/gpu/drm/mga/mga_state.c 	sarea_priv->last_frame.head = dev_priv->prim.tail;
sarea_priv        580 drivers/gpu/drm/mga/mga_state.c 	sarea_priv->last_frame.wrap = dev_priv->prim.last_wrap;
sarea_priv        626 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        636 drivers/gpu/drm/mga/mga_state.c 		MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
sarea_priv        639 drivers/gpu/drm/mga/mga_state.c 			if (i < sarea_priv->nbox) {
sarea_priv        641 drivers/gpu/drm/mga/mga_state.c 						   &sarea_priv->boxes[i]);
sarea_priv        654 drivers/gpu/drm/mga/mga_state.c 		} while (++i < sarea_priv->nbox);
sarea_priv        674 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        683 drivers/gpu/drm/mga/mga_state.c 		MGA_EMIT_STATE(dev_priv, sarea_priv->dirty);
sarea_priv        686 drivers/gpu/drm/mga/mga_state.c 			if (i < sarea_priv->nbox) {
sarea_priv        688 drivers/gpu/drm/mga/mga_state.c 						   &sarea_priv->boxes[i]);
sarea_priv        700 drivers/gpu/drm/mga/mga_state.c 		} while (++i < sarea_priv->nbox);
sarea_priv        723 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &dev_priv->sarea_priv->context_state;
sarea_priv        769 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        770 drivers/gpu/drm/mga/mga_state.c 	drm_mga_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        771 drivers/gpu/drm/mga/mga_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        772 drivers/gpu/drm/mga/mga_state.c 	int nbox = sarea_priv->nbox;
sarea_priv        830 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        835 drivers/gpu/drm/mga/mga_state.c 	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
sarea_priv        836 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
sarea_priv        844 drivers/gpu/drm/mga/mga_state.c 	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
sarea_priv        852 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        856 drivers/gpu/drm/mga/mga_state.c 	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
sarea_priv        857 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
sarea_priv        865 drivers/gpu/drm/mga/mga_state.c 	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
sarea_priv        975 drivers/gpu/drm/mga/mga_state.c 	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
sarea_priv        983 drivers/gpu/drm/mga/mga_state.c 	drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        989 drivers/gpu/drm/mga/mga_state.c 	if (sarea_priv->nbox > MGA_NR_SAREA_CLIPRECTS)
sarea_priv        990 drivers/gpu/drm/mga/mga_state.c 		sarea_priv->nbox = MGA_NR_SAREA_CLIPRECTS;
sarea_priv       1001 drivers/gpu/drm/mga/mga_state.c 	dev_priv->sarea_priv->dirty |= MGA_UPLOAD_CONTEXT;
sarea_priv        511 drivers/gpu/drm/r128/r128_cce.c 	dev_priv->sarea_priv =
sarea_priv        556 drivers/gpu/drm/r128/r128_cce.c 	dev_priv->sarea_priv->last_frame = 0;
sarea_priv        557 drivers/gpu/drm/r128/r128_cce.c 	R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
sarea_priv        559 drivers/gpu/drm/r128/r128_cce.c 	dev_priv->sarea_priv->last_dispatch = 0;
sarea_priv        560 drivers/gpu/drm/r128/r128_cce.c 	R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
sarea_priv         89 drivers/gpu/drm/r128/r128_drv.h 	drm_r128_sarea_t *sarea_priv;
sarea_priv        465 drivers/gpu/drm/r128/r128_drv.h 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;		\
sarea_priv        466 drivers/gpu/drm/r128/r128_drv.h 	if (sarea_priv->last_dispatch >= R128_MAX_VB_AGE) {		\
sarea_priv        470 drivers/gpu/drm/r128/r128_drv.h 		sarea_priv->last_dispatch = 0;				\
sarea_priv         91 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv         92 drivers/gpu/drm/r128/r128_state.c 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        106 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        107 drivers/gpu/drm/r128/r128_state.c 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        132 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        133 drivers/gpu/drm/r128/r128_state.c 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        148 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        149 drivers/gpu/drm/r128/r128_state.c 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        167 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        168 drivers/gpu/drm/r128/r128_state.c 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        182 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        183 drivers/gpu/drm/r128/r128_state.c 	drm_r128_context_regs_t *ctx = &sarea_priv->context_state;
sarea_priv        184 drivers/gpu/drm/r128/r128_state.c 	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0];
sarea_priv        208 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        209 drivers/gpu/drm/r128/r128_state.c 	drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1];
sarea_priv        230 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        231 drivers/gpu/drm/r128/r128_state.c 	unsigned int dirty = sarea_priv->dirty;
sarea_priv        237 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_CORE;
sarea_priv        242 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT;
sarea_priv        247 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_SETUP;
sarea_priv        252 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_MASKS;
sarea_priv        257 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_WINDOW;
sarea_priv        262 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_TEX0;
sarea_priv        267 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->dirty &= ~R128_UPLOAD_TEX1;
sarea_priv        271 drivers/gpu/drm/r128/r128_state.c 	sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH;
sarea_priv        273 drivers/gpu/drm/r128/r128_state.c 	sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE;
sarea_priv        362 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        363 drivers/gpu/drm/r128/r128_state.c 	int nbox = sarea_priv->nbox;
sarea_priv        364 drivers/gpu/drm/r128/r128_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        467 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        468 drivers/gpu/drm/r128/r128_state.c 	int nbox = sarea_priv->nbox;
sarea_priv        469 drivers/gpu/drm/r128/r128_state.c 	struct drm_clip_rect *pbox = sarea_priv->boxes;
sarea_priv        520 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->last_frame++;
sarea_priv        525 drivers/gpu/drm/r128/r128_state.c 	OUT_RING(dev_priv->sarea_priv->last_frame);
sarea_priv        535 drivers/gpu/drm/r128/r128_state.c 		  dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage);
sarea_priv        559 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->last_frame++;
sarea_priv        560 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
sarea_priv        566 drivers/gpu/drm/r128/r128_state.c 	OUT_RING(dev_priv->sarea_priv->last_frame);
sarea_priv        575 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        576 drivers/gpu/drm/r128/r128_state.c 	int format = sarea_priv->vc_format;
sarea_priv        582 drivers/gpu/drm/r128/r128_state.c 	DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox);
sarea_priv        585 drivers/gpu/drm/r128/r128_state.c 		r128_print_dirty("dispatch_vertex", sarea_priv->dirty);
sarea_priv        590 drivers/gpu/drm/r128/r128_state.c 		if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS)
sarea_priv        595 drivers/gpu/drm/r128/r128_state.c 			if (i < sarea_priv->nbox) {
sarea_priv        597 drivers/gpu/drm/r128/r128_state.c 						     &sarea_priv->boxes[i],
sarea_priv        598 drivers/gpu/drm/r128/r128_state.c 						     sarea_priv->nbox - i);
sarea_priv        614 drivers/gpu/drm/r128/r128_state.c 		} while (i < sarea_priv->nbox);
sarea_priv        618 drivers/gpu/drm/r128/r128_state.c 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
sarea_priv        634 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->last_dispatch++;
sarea_priv        636 drivers/gpu/drm/r128/r128_state.c 	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
sarea_priv        637 drivers/gpu/drm/r128/r128_state.c 	sarea_priv->nbox = 0;
sarea_priv        676 drivers/gpu/drm/r128/r128_state.c 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
sarea_priv        692 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->last_dispatch++;
sarea_priv        701 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv        702 drivers/gpu/drm/r128/r128_state.c 	int format = sarea_priv->vc_format;
sarea_priv        712 drivers/gpu/drm/r128/r128_state.c 		r128_print_dirty("dispatch_indices", sarea_priv->dirty);
sarea_priv        717 drivers/gpu/drm/r128/r128_state.c 		if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS)
sarea_priv        744 drivers/gpu/drm/r128/r128_state.c 			if (i < sarea_priv->nbox) {
sarea_priv        746 drivers/gpu/drm/r128/r128_state.c 						     &sarea_priv->boxes[i],
sarea_priv        747 drivers/gpu/drm/r128/r128_state.c 						     sarea_priv->nbox - i);
sarea_priv        753 drivers/gpu/drm/r128/r128_state.c 		} while (i < sarea_priv->nbox);
sarea_priv        757 drivers/gpu/drm/r128/r128_state.c 		buf_priv->age = dev_priv->sarea_priv->last_dispatch;
sarea_priv        772 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->last_dispatch++;
sarea_priv        774 drivers/gpu/drm/r128/r128_state.c 	sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS;
sarea_priv        775 drivers/gpu/drm/r128/r128_state.c 	sarea_priv->nbox = 0;
sarea_priv       1206 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv;
sarea_priv       1216 drivers/gpu/drm/r128/r128_state.c 	sarea_priv = dev_priv->sarea_priv;
sarea_priv       1218 drivers/gpu/drm/r128/r128_state.c 	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
sarea_priv       1219 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
sarea_priv       1226 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS;
sarea_priv       1245 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
sarea_priv       1294 drivers/gpu/drm/r128/r128_state.c 	drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv;
sarea_priv       1303 drivers/gpu/drm/r128/r128_state.c 	if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS)
sarea_priv       1304 drivers/gpu/drm/r128/r128_state.c 		sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS;
sarea_priv       1307 drivers/gpu/drm/r128/r128_state.c 	dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT |
sarea_priv        814 drivers/gpu/drm/savage/savage_bci.c 	dev_priv->sarea_priv =
sarea_priv        134 drivers/gpu/drm/savage/savage_drv.h 	drm_savage_sarea_t *sarea_priv;
sarea_priv         71 drivers/gpu/drm/via/via_drv.h 	drm_via_sarea_t *sarea_priv;
sarea_priv         61 drivers/gpu/drm/via/via_map.c 	dev_priv->sarea_priv =
sarea_priv         41 drivers/gpu/drm/via/via_video.c 		XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0;
sarea_priv         54 drivers/gpu/drm/via/via_video.c 	if (!dev_priv->sarea_priv)
sarea_priv         58 drivers/gpu/drm/via/via_video.c 		lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i);
sarea_priv         74 drivers/gpu/drm/via/via_video.c 	drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;