sar_base 62 arch/arm/mach-omap2/omap-mpuss-lowpower.c static void __iomem *sar_base; sar_base 200 arch/arm/mach-omap2/omap-mpuss-lowpower.c if (l2x0_base && sar_base) { sar_base 202 arch/arm/mach-omap2/omap-mpuss-lowpower.c sar_base + L2X0_AUXCTRL_OFFSET); sar_base 204 arch/arm/mach-omap2/omap-mpuss-lowpower.c sar_base + L2X0_PREFETCH_CTRL_OFFSET); sar_base 369 arch/arm/mach-omap2/omap-mpuss-lowpower.c if (sar_base) { sar_base 370 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->scu_sar_addr = sar_base + SCU_OFFSET0; sar_base 372 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->wkup_sar_addr = sar_base + sar_base 375 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->wkup_sar_addr = sar_base + sar_base 377 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0; sar_base 393 arch/arm/mach-omap2/omap-mpuss-lowpower.c if (sar_base) { sar_base 394 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->scu_sar_addr = sar_base + SCU_OFFSET1; sar_base 396 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->wkup_sar_addr = sar_base + sar_base 399 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->wkup_sar_addr = sar_base + sar_base 401 arch/arm/mach-omap2/omap-mpuss-lowpower.c pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1; sar_base 425 arch/arm/mach-omap2/omap-mpuss-lowpower.c if (sar_base) { sar_base 428 arch/arm/mach-omap2/omap-mpuss-lowpower.c sar_base + OMAP_TYPE_OFFSET); sar_base 470 arch/arm/mach-omap2/omap-mpuss-lowpower.c sar_base = omap4_get_sar_ram_base(); sar_base 474 arch/arm/mach-omap2/omap-mpuss-lowpower.c ns_pa_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET; sar_base 476 arch/arm/mach-omap2/omap-mpuss-lowpower.c ns_pa_addr = sar_base + OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET; sar_base 489 arch/arm/mach-omap2/omap-mpuss-lowpower.c writel_relaxed(startup_pa, sar_base + sar_base 492 arch/arm/mach-omap2/omap-mpuss-lowpower.c writel_relaxed(startup_pa, sar_base + sar_base 54 arch/arm/mach-omap2/omap-wakeupgen.c static void __iomem *sar_base; sar_base 89 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + offset + (idx * 4)); sar_base 265 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET); sar_base 267 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET); sar_base 271 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET); sar_base 273 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET); sar_base 276 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); sar_base 278 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET); sar_base 298 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET); sar_base 300 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET); sar_base 303 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); sar_base 305 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); sar_base 351 arch/arm/mach-omap2/omap-wakeupgen.c val = readl_relaxed(sar_base + offset); sar_base 353 arch/arm/mach-omap2/omap-wakeupgen.c writel_relaxed(val, sar_base + offset); sar_base 630 arch/arm/mach-omap2/omap-wakeupgen.c sar_base = omap4_get_sar_ram_base(); sar_base 274 arch/arm/mach-omap2/omap4-common.c unsigned long sar_base; sar_base 281 arch/arm/mach-omap2/omap4-common.c sar_base = OMAP44XX_SAR_RAM_BASE; sar_base 283 arch/arm/mach-omap2/omap4-common.c sar_base = OMAP54XX_SAR_RAM_BASE; sar_base 288 arch/arm/mach-omap2/omap4-common.c sar_ram_base = ioremap(sar_base, SZ_16K);